[PATCH] D70511: [BPF] Fix a bug in peephole optimization

[Yonghong Song via Phabricator via llvm-commits]

yonghong-song created this revision.
yonghong-song added a reviewer: ast.
Herald added subscribers: llvm-commits, hiraditya.
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One of current peephole optimiations is to remove SLL/SRL if
the sub register has been zero extended. This phase has two bugs
and one limitations.

First, for the physical subregister used in pseudo insn COPY
like below, it permits incorrect optimization.

  %0:gpr32 = COPY $w0 
  ... 
  %4:gpr = MOV_32_64 %0:gpr32
  %5:gpr = SLL_ri %4:gpr(tied-def 0), 32
  %6:gpr = SRA_ri %5:gpr(tied-def 0), 32

The $w0 could be from the return value of a previous function call
and its upper 32-bit value might contain some non-zero values.
The same applies to function arguments.

Second, the current code may permits removing SLL/SRA like below:

  %0:gpr32 = COPY $w0 
  %1:gpr32 = COPY %0:gpr32
  ... 
  %4:gpr = MOV_32_64 %1:gpr32
  %5:gpr = SLL_ri %4:gpr(tied-def 0), 32
  %6:gpr = SRA_ri %5:gpr(tied-def 0), 32

The reason is that it did not follow def-use chain to skip all 
intermediate 32bit-to-32bit COPY instructions.

The current implementation is also very conservative for PHI 
instructions. If any PHI insn component is another PHI or COPY insn,
it will just permit SLL/SRA.

This patch fixed the issue as follows:

- During def/use chain traversal, if any physical register is read, SLL/SRA will be preserved as these physical registers are mostly from function return values or current function arguments.
- Recursively visit all COPY and PHI instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70511

Files:
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
  llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-1.ll
  llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-2.ll
  llvm/test/CodeGen/BPF/32-bit-subreg-peephole.ll

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