[llvm] 824b25f - [Hexagon] Fix two testcase errors
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 20 13:07:11 PST 2019
Author: Krzysztof Parzyszek
Date: 2019-11-20T15:06:35-06:00
New Revision: 824b25fc02dc4544adae55e6451d355f4c6d7055
URL: https://github.com/llvm/llvm-project/commit/824b25fc02dc4544adae55e6451d355f4c6d7055
DIFF: https://github.com/llvm/llvm-project/commit/824b25fc02dc4544adae55e6451d355f4c6d7055.diff
LOG: [Hexagon] Fix two testcase errors
This fixes issues discovered in https://reviews.llvm.org/D63973.
Added:
Modified:
llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
llvm/test/CodeGen/Hexagon/sdr-global.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
index 2484f6b8fe68..e62cd1cc7360 100644
--- a/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
+++ b/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
@@ -16,7 +16,7 @@ body: |
%0:intregs = A2_tfrsi 0 ;; Multiple defs to ensure IsSSA = false
%0:intregs = L2_loadri_io $r0, 0
- %1:predregs = C2_cmplt %0, 10
+ %1:predregs = C2_cmpgti %0, 10
%2:intregs = C2_mux %1, $r31, %0
%3:predregs = C2_cmpeqi %2, 0
J2_jumpt %3, %bb.1, implicit-def $pc
diff --git a/llvm/test/CodeGen/Hexagon/sdr-global.mir b/llvm/test/CodeGen/Hexagon/sdr-global.mir
index dc55a9b71834..f5c5f46061a7 100644
--- a/llvm/test/CodeGen/Hexagon/sdr-global.mir
+++ b/llvm/test/CodeGen/Hexagon/sdr-global.mir
@@ -3,8 +3,8 @@
# This used to crash because the constant operand was not an immediate.
# Make sure we can handle such a case.
-# CHECK: = A2_tfrsi 0
-# CHECK: = A2_tfrsi @g0
+# CHECK-DAG: = A2_tfrsi 0
+# CHECK-DAG: = A2_tfrsi @g0
--- |
define i32 @fred() {
@@ -18,7 +18,7 @@ name: fred
tracksRegLiveness: true
body: |
bb.0:
- %0:doubleregs = A4_combineir 0, @g0
+ %0:doubleregs = A4_combineii 0, @g0
$r0 = COPY %0.isub_lo
PS_jmpret $r31, implicit-def $pc, implicit $r0
...
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