[PATCH] D63973: [MachineVerifier] Improve checks of target instructions operands.

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa updated this revision to Diff 230299.
jonpa added a comment.

XFAIL of AArch64 removed since it was fixed - thank you!

Sorry, I now see that with expensive checks enabled three more tests fail:

  LLVM :: CodeGen/Hexagon/vasrh.select.ll
  LLVM :: CodeGen/SPARC/fp128.ll
  LLVM :: CodeGen/SystemZ/htm-intrinsics.ll

CodeGen/Hexagon/vasrh.select.ll:

  # After Instruction Selection
  *** Bad machine code: Expected a register operand. ***
  - function:    f0
  - basic block: %bb.0 b0 (0x639e558)
  - instruction: %1:doubleregs = S2_asr_r_vh killed %0:doubleregs, 62
  - operand 2:   62
  LLVM ERROR: Found 1 machine code errors.

test/CodeGen/SPARC/fp128.ll

  # After Instruction Selection
  *** Bad machine code: Expected a register operand. ***
  - function:    f128_compare
  - basic block: %bb.0 entry (0x63ed058)
  - instruction: CMPrr killed %21:intregs, 0, implicit-def $icc
  - operand 1:   0
  LLVM ERROR: Found 1 machine code errors.

I have proposed a patch for the SystemZ test case at https://reviews.llvm.org/D70501.

Hexagon test failures  (all three) reported at https://bugs.llvm.org/show_bug.cgi?id=44090
SPARC failure reported at https://bugs.llvm.org/show_bug.cgi?id=44091

Would it be ok to XFAIL also the test cases that fail only with expensive checks enabled and then commit?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63973/new/

https://reviews.llvm.org/D63973

Files:
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
  llvm/test/CodeGen/Hexagon/sdr-global.mir
  llvm/test/MachineVerifier/verify-regops.mir

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