[PATCH] D70501: [SystemZ] Don't build a PPA instruction with an immediate 0

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa created this revision.
jonpa added a reviewer: uweigand.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

The improvement in the machine verifier for operand types (D63973 <https://reviews.llvm.org/D63973>) discovered a bad operand in a test using a PPA instruction. It was an immediate 0 where a register was expected.

This patch is an attempt to remedy this by using the same register in the second operand as in the first and then emitting instead %R0D in the assembly printer. I first tried to do away with the second register operand and just printing 0, but then some MC tests failed, so it seems we do need to model the second operand as a register to have all parts working.

This patch in fact improves things a bit, since currently it doesn't work to do

  llc ~/llvm-project/llvm/test/CodeGen/SystemZ/htm-intrinsics.ll -mtriple=s390x-linux-gnu -mcpu=zEC12 -o out.s
  llvm-mc -mcpu=zEC12 out.s --show-encoding
  out.s:403:11: error: invalid operand for instruction
          ppa     %r2, 0, 1
                       ^


https://reviews.llvm.org/D70501

Files:
  llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
  llvm/lib/Target/SystemZ/SystemZInstrInfo.td
  llvm/test/CodeGen/SystemZ/htm-intrinsics.ll


Index: llvm/test/CodeGen/SystemZ/htm-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/SystemZ/htm-intrinsics.ll
+++ llvm/test/CodeGen/SystemZ/htm-intrinsics.ll
@@ -344,7 +344,7 @@
 ; PPA (Transaction-Abort Assist)
 define void @test_ppa_txassist(i32 %val) {
 ; CHECK-LABEL: test_ppa_txassist:
-; CHECK: ppa %r2, 0, 1
+; CHECK: ppa %r2, %r0, 1
 ; CHECK: br %r14
   call void @llvm.s390.ppa.txassist(i32 %val)
   ret void
Index: llvm/lib/Target/SystemZ/SystemZInstrInfo.td
===================================================================
--- llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2064,12 +2064,16 @@
 // Processor assist
 //===----------------------------------------------------------------------===//
 
+// The second register operand is ignored but should be 0 in the output. Let
+// the second operand use the same reg as the first one and then emit %R0D in
+// the AsmPrinter. This avoids a false use of %R0D during compilation.
 let Predicates = [FeatureProcessorAssist] in {
   let hasSideEffects = 1 in
     def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>;
   def : Pat<(int_s390_ppa_txassist GR32:$src),
             (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
-                 0, 1)>;
+                 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
+                 1)>;
 }
 
 //===----------------------------------------------------------------------===//
Index: llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
===================================================================
--- llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -501,6 +501,13 @@
     }
     break;
 
+  case SystemZ::PPA:
+    LoweredMI = MCInstBuilder(SystemZ::PPA)
+      .addReg(MI->getOperand(0).getReg())
+      .addReg(SystemZ::R0D)
+      .addImm(MI->getOperand(2).getImm());
+    break;
+
   case TargetOpcode::FENTRY_CALL:
     LowerFENTRY_CALL(*MI, Lower);
     return;


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