[PATCH] D70431: [DebugInfo] Make describeLoadedValue() reg aware

[David Stenberg via Phabricator via llvm-commits]

dstenb marked an inline comment as done.
dstenb added inline comments.


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Comment at: llvm/lib/CodeGen/TargetInstrInfo.cpp:1174
+    // zero-extending add immediate.
+    if (TRI->isSuperRegisterEq(DestReg, Reg) && MI.definesRegister(Reg, TRI))
+      return ParamLoadedValue(*Source, Expr);
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vsk wrote:
> vsk wrote:
> > Ditto, not sure why 'isSuperRegister' isn't enough here.
> Ditto, why is it safe to assume this is a zero-extending add? E.g. I think 'sxta' on ARM works differently.
Looking around at a few target, it seemed like in such cases the whole extended super-register would be the explicit define, but I guess there's nothing that says that that must be the case.

I'll look into adding a Register parameter to isAddImmediate(), and let that handle whether or not super-registers can be described (and if so, if the value should be sign-extended).


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D70431/new/

https://reviews.llvm.org/D70431