[PATCH] D70466: [PowerPC] Separate Features that are known to be Power9 specific from Future CPU

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.
stefanp added reviewers: lei, nemanjai, hfinkel, power-llvm-team, jsji, PowerPC.
Herald added subscribers: shchenz, kbarton, hiraditya.
Herald added a project: LLVM.
stefanp added a parent revision: D70333: [PowerPC] Add new Future CPU for PowerPC in LLVM.
Herald added a subscriber: wuzish.

The Power 9 CPU has some features that are unlikely to be passed on to future versions of the CPU.
This patch separates this out so that future CPU does not inherit them.


https://reviews.llvm.org/D70466

Files:
  llvm/lib/Target/PowerPC/PPC.td
  llvm/test/Analysis/CostModel/PowerPC/future-cost-model.ll


Index: llvm/test/Analysis/CostModel/PowerPC/future-cost-model.ll
===================================================================
--- /dev/null
+++ llvm/test/Analysis/CostModel/PowerPC/future-cost-model.ll
@@ -0,0 +1,16 @@
+; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:       -mcpu=future | FileCheck %s --check-prefix=FUTURE
+; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:       -mcpu=pwr9 | FileCheck %s --check-prefix=PWR9
+
+define void @test(i16 %p1, i16 %p2, <4 x i16> %p3, <4 x i16> %p4) {
+  %i1 = add i16 %p1, %p2
+  %v1 = add <4 x i16> %p3, %p4
+  ret void
+  ; FUTURE: cost of 1 {{.*}} add
+  ; FUTURE: cost of 1 {{.*}} add
+
+  ; PWR9: cost of 1 {{.*}} add
+  ; PWR9: cost of 2 {{.*}} add
+}
+
Index: llvm/lib/Target/PowerPC/PPC.td
===================================================================
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -237,13 +237,16 @@
   list<SubtargetFeature> Power8FeatureList =
       !listconcat(Power7FeatureList, Power8SpecificFeatures);
   list<SubtargetFeature> Power9SpecificFeatures =
-      [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0,
-       FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched];
+      [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0];
+  list<SubtargetFeature> Power9OnlyFeatures =
+      [FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched];
   list<SubtargetFeature> Power9FeatureList =
       !listconcat(Power8FeatureList, Power9SpecificFeatures);
+  list<SubtargetFeature> Power9ImplList =
+      !listconcat(Power9FeatureList, Power9OnlyFeatures);
 
   // For future CPU we assume that all of the existing features from Power 9
-  // still exist.
+  // still exist with the exception of those we know are Power 9 specific.
   list<SubtargetFeature> FutureSpecificFeatures =
       [];
   list<SubtargetFeature> FutureFeatureList =
@@ -449,7 +452,7 @@
                    FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
-def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;
+def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9ImplList>;
 // No scheduler model for future CPU.
 def : ProcessorModel<"future", NoSchedModel,
                   ProcessorFeatures.FutureFeatureList>;


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