[PATCH] D70181: [MVE] [ARM] Select VQABS

[Anna Welker via Phabricator via llvm-commits]

anwel marked 2 inline comments as done.
anwel added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:1962
+    def : Pat<(VTI.Vec (vselect
+                      (VTI.Pred (ARMvcmpz (VTI.Vec MQPR:$reg), (i32 12))),
+                      (VTI.Vec MQPR:$reg),
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simon_tatham wrote:
> This `(i32 12)`, and the `(i32 0)` in the `ARMvcmp` a couple of lines below, are the only remaining magic numbers that have no explanation here. I think they deserve a comment explaining them: 12 and 0 are respectively the Arm architecture's condition-code encodings for GT and EQ, so this `ARMvcmpz` is testing if each lane is //greater than// zero, and the `ARMvcmp` below is testing if each lane is //equal to// (the corresponding lane of) `int_min`.
Thanks for reminding me, I decided to just add a comment that explains what expression the tree structure will match - hopefully that should make it clear what happens.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70181/new/

https://reviews.llvm.org/D70181