[llvm] 1ce5fcd - [PowerPC] [NFC] add IR testcases for folding rlwinma.

[via llvm-commits]

Author: czhengsz
Date: 2019-11-18T07:43:30-05:00
New Revision: 1ce5fcda17e6683bcbec8585349afcad02a9c98a

URL: https://github.com/llvm/llvm-project/commit/1ce5fcda17e6683bcbec8585349afcad02a9c98a
DIFF: https://github.com/llvm/llvm-project/commit/1ce5fcda17e6683bcbec8585349afcad02a9c98a.diff

LOG: [PowerPC] [NFC] add IR testcases for folding rlwinma.

Added: 
    llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll b/llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll
new file mode 100644
index 000000000000..b0586b06cd1f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
+
+ at res = dso_local local_unnamed_addr global i32 0, align 4
+ at res2 = dso_local local_unnamed_addr global i32 0, align 4
+
+define void @foo(i32 signext %var1) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    addis r4, r2, res at toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    slwi r3, r3, 19
+; CHECK-NEXT:    stw r3, res at toc@l(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %var1, 1
+  %conv = zext i1 %cmp to i32
+  %shl = shl nuw nsw i32 %conv, 19
+  store i32 %shl, i32* @res, align 4
+  ret void
+}
+
+define void @foo_multiple_use(i32 signext %var1) {
+; CHECK-LABEL: foo_multiple_use:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    addis r4, r2, res2 at toc@ha
+; CHECK-NEXT:    addis r6, r2, res at toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    slwi r5, r3, 19
+; CHECK-NEXT:    stw r3, res2 at toc@l(r4)
+; CHECK-NEXT:    stw r5, res at toc@l(r6)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %var1, 1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @res2, align 4
+  %shl = shl nuw nsw i32 %conv, 19
+  store i32 %shl, i32* @res, align 4
+  ret void
+}