[llvm] eedb964 - [RISCV] Add assembly mnemonic spell checking

[Simon Cook via llvm-commits]

Author: Simon Cook
Date: 2019-11-18T10:58:00Z
New Revision: eedb9648229ff14bf8d5a526099f765ea23f3777

URL: https://github.com/llvm/llvm-project/commit/eedb9648229ff14bf8d5a526099f765ea23f3777
DIFF: https://github.com/llvm/llvm-project/commit/eedb9648229ff14bf8d5a526099f765ea23f3777.diff

LOG: [RISCV] Add assembly mnemonic spell checking

Summary:
This allows the assembler to suggest alternative assembly mnemonics when
an invalid one has been provided.

Reviewers: asb, lenary, lewis-revill

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69894

Added: 
    llvm/test/MC/RISCV/invalid-instruction-spellcheck.s

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 300ba8dc675c..ebc9a61e6b9b 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -739,6 +739,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
 
 #define GET_REGISTER_MATCHER
 #define GET_MATCHER_IMPLEMENTATION
+#define GET_MNEMONIC_SPELL_CHECKER
 #include "RISCVGenAsmMatcher.inc"
 
 static Register convertFPR64ToFPR32(Register Reg) {
@@ -775,6 +776,10 @@ bool RISCVAsmParser::generateImmOutOfRangeError(
   return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]");
 }
 
+static std::string RISCVMnemonicSpellCheck(StringRef S,
+                                          const FeatureBitset &FBS,
+                                          unsigned VariantID = 0);
+
 bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                              OperandVector &Operands,
                                              MCStreamer &Out,
@@ -791,8 +796,12 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     return processInstruction(Inst, IDLoc, Operands, Out);
   case Match_MissingFeature:
     return Error(IDLoc, "instruction use requires an option to be enabled");
-  case Match_MnemonicFail:
-    return Error(IDLoc, "unrecognized instruction mnemonic");
+  case Match_MnemonicFail: {
+    FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
+    std::string Suggestion = RISCVMnemonicSpellCheck(
+      ((RISCVOperand &)*Operands[0]).getToken(), FBS);
+    return Error(IDLoc, "unrecognized instruction mnemonic" + Suggestion);
+  }
   case Match_InvalidOperand: {
     SMLoc ErrorLoc = IDLoc;
     if (ErrorInfo != ~0U) {

diff  --git a/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s b/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s
new file mode 100644
index 000000000000..c5c0d2f3a0b1
--- /dev/null
+++ b/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s
@@ -0,0 +1,32 @@
+# RUN: not llvm-mc -triple=riscv32 < %s 2>&1 \
+# RUN:         | FileCheck -check-prefixes=CHECK,CHECK-RV32,CHECK-RV32I %s
+# RUN: not llvm-mc -triple=riscv64 < %s 2>&1 \
+# RUN:         | FileCheck -check-prefixes=CHECK,CHECK-RV64,CHECK-RV64I %s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+f < %s 2>&1 \
+# RUN:         | FileCheck -check-prefixes=CHECK,CHECK-RV32,CHECK-RV32IF %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+f < %s 2>&1 \
+# RUN:         | FileCheck -check-prefixes=CHECK,CHECK-RV64,CHECK-RV64IF %s
+
+# Tests for the mnemonic spell checker. Suggestions should only include those
+# which are valid for the current set of features
+
+ad x1, x1, x1
+# CHECK-RV32: did you mean: add, addi, and, andi, la
+# CHECK-RV64: did you mean: add, addi, addw, and, andi, la, ld, sd
+# CHECK-NEXT: ad x1, x1, x1
+
+fl ft0, 0(sp)
+# CHECK-RV32I: did you mean: la, lb, lh, li, lw
+# CHECK-RV32IF: did you mean: flw, la, lb, lh, li, lw
+# CHECK-RV64I: did you mean: la, lb, ld, lh, li, lw
+# CHECK-RV64IF: did you mean: flw, la, lb, ld, lh, li, lw
+# CHECK-NEXT: fl ft0, 0(sp)
+
+addd x1, x1, x1
+# CHECK-RV32: did you mean: add, addi
+# CHECK-RV64: did you mean: add, addi, addw
+# CHECK-NEXT: addd x1, x1, x1
+
+vm x0, x0
+# CHECK: did you mean: mv
+# CHECK-NEXT: vm x0, x0