[llvm] 03e7fb2 - [NFC][Test] Add the vavg test for PowerPC
QingShan Zhang via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 18 02:42:01 PST 2019
Author: QingShan Zhang
Date: 2019-11-18T10:41:47Z
New Revision: 03e7fb2e075e2cfca7a0c9e3730a48d52101dec2
URL: https://github.com/llvm/llvm-project/commit/03e7fb2e075e2cfca7a0c9e3730a48d52101dec2
DIFF: https://github.com/llvm/llvm-project/commit/03e7fb2e075e2cfca7a0c9e3730a48d52101dec2.diff
LOG: [NFC][Test] Add the vavg test for PowerPC
Added:
llvm/test/CodeGen/PowerPC/vavg.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/vavg.ll b/llvm/test/CodeGen/PowerPC/vavg.ll
new file mode 100644
index 000000000000..ad6c1c844dea
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vavg.ll
@@ -0,0 +1,189 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-P7 %s
+define <8 x i16> @test_v8i16(<8 x i16> %m, <8 x i16> %n) {
+; CHECK-P9-LABEL: test_v8i16:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: xxlnor 34, 34, 34
+; CHECK-P9-NEXT: vspltish 4, 1
+; CHECK-P9-NEXT: vsubuhm 2, 3, 2
+; CHECK-P9-NEXT: vsrh 2, 2, 4
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: test_v8i16:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: xxlnor 34, 34, 34
+; CHECK-P8-NEXT: vspltish 4, 1
+; CHECK-P8-NEXT: vsubuhm 2, 3, 2
+; CHECK-P8-NEXT: vsrh 2, 2, 4
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P7-LABEL: test_v8i16:
+; CHECK-P7: # %bb.0: # %entry
+; CHECK-P7-NEXT: xxlnor 34, 34, 34
+; CHECK-P7-NEXT: vspltish 4, 1
+; CHECK-P7-NEXT: vsubuhm 2, 3, 2
+; CHECK-P7-NEXT: vsrh 2, 2, 4
+; CHECK-P7-NEXT: blr
+entry:
+ %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %add1 = add <8 x i16> %add, %n
+ %shr = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ ret <8 x i16> %shr
+}
+
+define <8 x i16> @test_v8i16_sign(<8 x i16> %m, <8 x i16> %n) {
+; CHECK-P9-LABEL: test_v8i16_sign:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: xxlnor 34, 34, 34
+; CHECK-P9-NEXT: vspltish 4, 1
+; CHECK-P9-NEXT: vsubuhm 2, 3, 2
+; CHECK-P9-NEXT: vsrah 2, 2, 4
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: test_v8i16_sign:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: xxlnor 34, 34, 34
+; CHECK-P8-NEXT: vspltish 4, 1
+; CHECK-P8-NEXT: vsubuhm 2, 3, 2
+; CHECK-P8-NEXT: vsrah 2, 2, 4
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P7-LABEL: test_v8i16_sign:
+; CHECK-P7: # %bb.0: # %entry
+; CHECK-P7-NEXT: xxlnor 34, 34, 34
+; CHECK-P7-NEXT: vspltish 4, 1
+; CHECK-P7-NEXT: vsubuhm 2, 3, 2
+; CHECK-P7-NEXT: vsrah 2, 2, 4
+; CHECK-P7-NEXT: blr
+entry:
+ %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %add1 = add <8 x i16> %add, %n
+ %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ ret <8 x i16> %shr
+}
+
+define <4 x i32> @test_v4i32(<4 x i32> %m, <4 x i32> %n) {
+; CHECK-P9-LABEL: test_v4i32:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: xxlnor 34, 34, 34
+; CHECK-P9-NEXT: vspltisw 4, 1
+; CHECK-P9-NEXT: vsubuwm 2, 3, 2
+; CHECK-P9-NEXT: vsrw 2, 2, 4
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: test_v4i32:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: xxlnor 34, 34, 34
+; CHECK-P8-NEXT: vspltisw 4, 1
+; CHECK-P8-NEXT: vsubuwm 2, 3, 2
+; CHECK-P8-NEXT: vsrw 2, 2, 4
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P7-LABEL: test_v4i32:
+; CHECK-P7: # %bb.0: # %entry
+; CHECK-P7-NEXT: xxlnor 34, 34, 34
+; CHECK-P7-NEXT: vspltisw 4, 1
+; CHECK-P7-NEXT: vsubuwm 2, 3, 2
+; CHECK-P7-NEXT: vsrw 2, 2, 4
+; CHECK-P7-NEXT: blr
+entry:
+ %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>
+ %add1 = add <4 x i32> %add, %n
+ %shr = lshr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %shr
+}
+
+define <4 x i32> @test_v4i32_sign(<4 x i32> %m, <4 x i32> %n) {
+; CHECK-P9-LABEL: test_v4i32_sign:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: xxlnor 34, 34, 34
+; CHECK-P9-NEXT: vspltisw 4, 1
+; CHECK-P9-NEXT: vsubuwm 2, 3, 2
+; CHECK-P9-NEXT: vsraw 2, 2, 4
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: test_v4i32_sign:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: xxlnor 34, 34, 34
+; CHECK-P8-NEXT: vspltisw 4, 1
+; CHECK-P8-NEXT: vsubuwm 2, 3, 2
+; CHECK-P8-NEXT: vsraw 2, 2, 4
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P7-LABEL: test_v4i32_sign:
+; CHECK-P7: # %bb.0: # %entry
+; CHECK-P7-NEXT: xxlnor 34, 34, 34
+; CHECK-P7-NEXT: vspltisw 4, 1
+; CHECK-P7-NEXT: vsubuwm 2, 3, 2
+; CHECK-P7-NEXT: vsraw 2, 2, 4
+; CHECK-P7-NEXT: blr
+entry:
+ %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>
+ %add1 = add <4 x i32> %add, %n
+ %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %shr
+}
+
+define <16 x i8> @test_v16i8(<16 x i8> %m, <16 x i8> %n) {
+; CHECK-P9-LABEL: test_v16i8:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: xxlnor 34, 34, 34
+; CHECK-P9-NEXT: xxspltib 36, 1
+; CHECK-P9-NEXT: vsububm 2, 3, 2
+; CHECK-P9-NEXT: vsrb 2, 2, 4
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: test_v16i8:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: xxlnor 34, 34, 34
+; CHECK-P8-NEXT: vspltisb 4, 1
+; CHECK-P8-NEXT: vsububm 2, 3, 2
+; CHECK-P8-NEXT: vsrb 2, 2, 4
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P7-LABEL: test_v16i8:
+; CHECK-P7: # %bb.0: # %entry
+; CHECK-P7-NEXT: xxlnor 34, 34, 34
+; CHECK-P7-NEXT: vspltisb 4, 1
+; CHECK-P7-NEXT: vsububm 2, 3, 2
+; CHECK-P7-NEXT: vsrb 2, 2, 4
+; CHECK-P7-NEXT: blr
+entry:
+ %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %add1 = add <16 x i8> %add, %n
+ %shr = lshr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ ret <16 x i8> %shr
+}
+
+define <16 x i8> @test_v16i8_sign(<16 x i8> %m, <16 x i8> %n) {
+; CHECK-P9-LABEL: test_v16i8_sign:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: xxlnor 34, 34, 34
+; CHECK-P9-NEXT: xxspltib 36, 1
+; CHECK-P9-NEXT: vsububm 2, 3, 2
+; CHECK-P9-NEXT: vsrab 2, 2, 4
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: test_v16i8_sign:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: xxlnor 34, 34, 34
+; CHECK-P8-NEXT: vspltisb 4, 1
+; CHECK-P8-NEXT: vsububm 2, 3, 2
+; CHECK-P8-NEXT: vsrab 2, 2, 4
+; CHECK-P8-NEXT: blr
+;
+; CHECK-P7-LABEL: test_v16i8_sign:
+; CHECK-P7: # %bb.0: # %entry
+; CHECK-P7-NEXT: xxlnor 34, 34, 34
+; CHECK-P7-NEXT: vspltisb 4, 1
+; CHECK-P7-NEXT: vsububm 2, 3, 2
+; CHECK-P7-NEXT: vsrab 2, 2, 4
+; CHECK-P7-NEXT: blr
+entry:
+ %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %add1 = add <16 x i8> %add, %n
+ %shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ ret <16 x i8> %shr
+}
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