[PATCH] D70379: [AMDGPU] Reserving VGPR for future SGPR Spill
Saiyedul Islam via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 18 02:01:31 PST 2019
saiislam created this revision.
saiislam added reviewers: arsenm, rampitec, msearles.
saiislam added a project: AMDGPU.
Herald added subscribers: llvm-commits, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.
VGPR register is allocated to handle a future spill of SGPR.
https://reviews.llvm.org/D70379
Files:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -100,6 +100,11 @@
cl::desc("Do not align and prefetch loops"),
cl::init(false));
+static cl::opt<bool> VGPRReserveforSGPRSpill(
+ "amdgpu-reserve-vgpr-for-sgpr-spill",
+ cl::desc("Allocates one VGPR for future SGPR Spill"),
+ cl::init(false));
+
static unsigned findFirstFreeSGPR(CCState &CCInfo) {
unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
@@ -10745,6 +10750,7 @@
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
+
if (Info->isEntryFunction()) {
// Callable functions have fixed registers used for stack access.
reservePrivateMemoryRegs(getTargetMachine(), MF, *TRI, *Info);
@@ -10790,6 +10796,15 @@
}
TargetLoweringBase::finalizeLowering(MF);
+
+ // Allocate a VGPR for future SGPR Spill if
+ // "amdgpu-reserve-vgpr-for-sgpr-spill" option is used
+ if (VGPRReserveforSGPRSpill) {
+ int fi = MF.getFrameInfo().CreateStackObject(4,4,false, nullptr, TargetStackID::SGPRSpill);
+ Info->allocateSGPRSpillToVGPR(MF, fi);
+ MF.getFrameInfo().RemoveStackObject(fi);
+ }
+
}
void SITargetLowering::computeKnownBitsForFrameIndex(const SDValue Op,
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