[llvm] 816ff98 - [Sparc] Fix "Cannot select" error for AtomicFence on 32-bit V9
James Clarke via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 18 01:46:25 PST 2019
Author: James Clarke
Date: 2019-11-18T09:45:10Z
New Revision: 816ff985f51ea984139c0b141d402e0143bd9f2d
URL: https://github.com/llvm/llvm-project/commit/816ff985f51ea984139c0b141d402e0143bd9f2d
DIFF: https://github.com/llvm/llvm-project/commit/816ff985f51ea984139c0b141d402e0143bd9f2d.diff
LOG: [Sparc] Fix "Cannot select" error for AtomicFence on 32-bit V9
Summary:
This also adds testing of 32-bit V9 atomic lowering, splitting the
64-bit-only tests out into their own file.
Reviewers: venkatra, jyknight
Reviewed By: jyknight
Subscribers: hiraditya, fedor.sergeev, jfb, llvm-commits, glaubitz
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69352
Added:
llvm/test/CodeGen/SPARC/64atomics.ll
Modified:
llvm/lib/Target/Sparc/SparcInstr64Bit.td
llvm/lib/Target/Sparc/SparcInstrInfo.td
llvm/test/CodeGen/SPARC/atomics.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
index d18ab3b1370b..9a200a36cd3e 100644
--- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td
+++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
@@ -497,8 +497,6 @@ let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
let Predicates = [Is64Bit] in {
-def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
-
// atomic_load_64 addr -> load addr
def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 73dbdc4f443e..7ebfef4ced8d 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -1678,6 +1678,9 @@ def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
let Predicates = [HasNoV9] in
def : Pat<(atomic_fence imm, imm), (STBAR)>;
+let Predicates = [HasV9] in
+ def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
+
// atomic_load addr -> load addr
def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
diff --git a/llvm/test/CodeGen/SPARC/64atomics.ll b/llvm/test/CodeGen/SPARC/64atomics.ll
new file mode 100644
index 000000000000..89175b6242e6
--- /dev/null
+++ b/llvm/test/CodeGen/SPARC/64atomics.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
+
+; CHECK-LABEL: test_atomic_i64
+; CHECK: ldx [%o0]
+; CHECK: membar
+; CHECK: ldx [%o1]
+; CHECK: membar
+; CHECK: membar
+; CHECK: stx {{.+}}, [%o2]
+define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
+entry:
+ %0 = load atomic i64, i64* %ptr1 acquire, align 8
+ %1 = load atomic i64, i64* %ptr2 acquire, align 8
+ %2 = add i64 %0, %1
+ store atomic i64 %2, i64* %ptr3 release, align 8
+ ret i64 %2
+}
+
+; CHECK-LABEL: test_cmpxchg_i64
+; CHECK: mov 123, [[R:%[gilo][0-7]]]
+; CHECK: casx [%o1], %o0, [[R]]
+
+define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
+entry:
+ %pair = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic monotonic
+ %b = extractvalue { i64, i1 } %pair, 0
+ ret i64 %b
+}
+
+; CHECK-LABEL: test_swap_i64
+; CHECK: casx [%o1],
+
+define i64 @test_swap_i64(i64 %a, i64* %ptr) {
+entry:
+ %b = atomicrmw xchg i64* %ptr, i64 42 monotonic
+ ret i64 %b
+}
+
+; CHECK-LABEL: test_load_sub_64
+; CHECK: membar
+; CHECK: sub
+; CHECK: casx [%o0]
+; CHECK: membar
+define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
+entry:
+ %0 = atomicrmw sub i64* %p, i64 %v seq_cst
+ ret i64 %0
+}
+
+; CHECK-LABEL: test_load_max_64
+; CHECK: membar
+; CHECK: cmp
+; CHECK: movg %xcc
+; CHECK: casx [%o0]
+; CHECK: membar
+define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
+entry:
+ %0 = atomicrmw max i64* %p, i64 %v seq_cst
+ ret i64 %0
+}
diff --git a/llvm/test/CodeGen/SPARC/atomics.ll b/llvm/test/CodeGen/SPARC/atomics.ll
index 17aa227ec9ac..c6ecbaf911dd 100644
--- a/llvm/test/CodeGen/SPARC/atomics.ll
+++ b/llvm/test/CodeGen/SPARC/atomics.ll
@@ -1,3 +1,4 @@
+; RUN: llc < %s -march=sparc -mcpu=v9 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: test_atomic_i8
@@ -48,22 +49,6 @@ entry:
ret i32 %2
}
-; CHECK-LABEL: test_atomic_i64
-; CHECK: ldx [%o0]
-; CHECK: membar
-; CHECK: ldx [%o1]
-; CHECK: membar
-; CHECK: membar
-; CHECK: stx {{.+}}, [%o2]
-define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
-entry:
- %0 = load atomic i64, i64* %ptr1 acquire, align 8
- %1 = load atomic i64, i64* %ptr2 acquire, align 8
- %2 = add i64 %0, %1
- store atomic i64 %2, i64* %ptr3 release, align 8
- ret i64 %2
-}
-
;; TODO: the "move %icc" and related instructions are totally
;; redundant here. There's something weird happening in optimization
;; of the success value of cmpxchg.
@@ -159,17 +144,6 @@ entry:
ret i32 %b
}
-; CHECK-LABEL: test_cmpxchg_i64
-; CHECK: mov 123, [[R:%[gilo][0-7]]]
-; CHECK: casx [%o1], %o0, [[R]]
-
-define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
-entry:
- %pair = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic monotonic
- %b = extractvalue { i64, i1 } %pair, 0
- ret i64 %b
-}
-
; CHECK-LABEL: test_swap_i8
; CHECK: mov 42, [[R:%[gilo][0-7]]]
; CHECK: cas
@@ -200,15 +174,6 @@ entry:
ret i32 %b
}
-; CHECK-LABEL: test_swap_i64
-; CHECK: casx [%o1],
-
-define i64 @test_swap_i64(i64 %a, i64* %ptr) {
-entry:
- %b = atomicrmw xchg i64* %ptr, i64 42 monotonic
- ret i64 %b
-}
-
; CHECK-LABEL: test_load_sub_i8
; CHECK: membar
; CHECK: .L{{.*}}:
@@ -246,17 +211,6 @@ entry:
ret i32 %0
}
-; CHECK-LABEL: test_load_sub_64
-; CHECK: membar
-; CHECK: sub
-; CHECK: casx [%o0]
-; CHECK: membar
-define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
-entry:
- %0 = atomicrmw sub i64* %p, i64 %v seq_cst
- ret i64 %0
-}
-
; CHECK-LABEL: test_load_xor_32
; CHECK: membar
; CHECK: xor
@@ -292,18 +246,6 @@ entry:
ret i32 %0
}
-; CHECK-LABEL: test_load_max_64
-; CHECK: membar
-; CHECK: cmp
-; CHECK: movg %xcc
-; CHECK: casx [%o0]
-; CHECK: membar
-define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
-entry:
- %0 = atomicrmw max i64* %p, i64 %v seq_cst
- ret i64 %0
-}
-
; CHECK-LABEL: test_load_umin_32
; CHECK: membar
; CHECK: cmp
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