[llvm] cc6b853 - [MIRNamer]: Make the check lines in the test robust with regex.
Aditya Nandakumar via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 16 23:01:39 PST 2019
Author: Aditya Nandakumar
Date: 2019-11-16T22:58:45-08:00
New Revision: cc6b85390170725d2341416af2b2ab8ea6c25d83
URL: https://github.com/llvm/llvm-project/commit/cc6b85390170725d2341416af2b2ab8ea6c25d83
DIFF: https://github.com/llvm/llvm-project/commit/cc6b85390170725d2341416af2b2ab8ea6c25d83.diff
LOG: [MIRNamer]: Make the check lines in the test robust with regex.
Previously we were checking for specific hashes. Make it check for
regexes.
Should fix failure caused by: 72768685567b
Added:
Modified:
llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir b/llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
index 41396b5ba7b7..e95b838030c7 100644
--- a/llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
@@ -39,8 +39,8 @@ body: |
%42:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
- ;CHECK: %bb0_11909__1:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
- ;CHECK-NEXT: $w0 = COPY %bb0_11909__1
+ ;CHECK: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+ ;CHECK-NEXT: $w0 = COPY %bb0_
;CHECK-NEXT: RET_ReallyLR implicit $w0
%vreg1234:gpr32 = COPY %42
diff --git a/llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir b/llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
index d393e80df98b..74eae56f9cb6 100644
--- a/llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
@@ -1,11 +1,11 @@
# RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -verify-machineinstrs -run-pass mir-canonicalizer %s | FileCheck %s
# These Idempotent instructions are sorted alphabetically (based on after the '=')
-# CHECK: %bb0_17169__1:gpr64 = MOVi64imm 4617315517961601024
-# CHECK-NEXT: %bb0_42274__1:gpr32 = MOVi32imm 408
-# CHECK-NEXT: %bb0_42274__2:gpr32 = MOVi32imm 408
-# CHECK-NEXT: %bb0_18275__1:gpr64all = IMPLICIT_DEF
-# CHECK-NEXT: %bb0_13880__1:fpr64 = FMOVDi 20
-# CHECK-NEXT: %bb0_21467__1:fpr64 = FMOVDi 112
+# CHECK: %bb0_{{[0-9]+}}__1:gpr64 = MOVi64imm 4617315517961601024
+# CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 408
+# CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = MOVi32imm 408
+# CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr64all = IMPLICIT_DEF
+# CHECK-NEXT: %bb0_{{[0-9]+}}__1:fpr64 = FMOVDi 20
+# CHECK-NEXT: %bb0_{{[0-9]+}}__1:fpr64 = FMOVDi 112
...
---
diff --git a/llvm/test/CodeGen/MIR/AArch64/mirnamer.mir b/llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
index e106e107616f..5d63f4107b92 100644
--- a/llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
@@ -6,9 +6,9 @@ body: |
bb.0:
;CHECK-LABEL: bb.0
- ;CHECK-NEXT: %bb0_12265__1:_(p0) = COPY $d0
- ;CHECK-NEXT: %bb0_18308__1:_(<4 x s32>) = COPY $q0
- ;CHECK-NEXT: G_STORE %bb0_18308__1(<4 x s32>), %bb0_12265__1(p0) :: (store 16)
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(p0) = COPY $d0
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(<4 x s32>) = COPY $q0
+ ;CHECK-NEXT: G_STORE %bb0_{{[0-9]+}}__1(<4 x s32>), %bb0_{{[0-9]+}}__1(p0) :: (store 16)
liveins: $q0, $d0
%1:fpr(p0) = COPY $d0
@@ -26,19 +26,19 @@ body: |
bb.0:
;CHECK-LABEL: bb.0
- ;CHECK-NEXT: %bb0_11909__1:gpr32 = LDRWui
- ;CHECK-NEXT: %bb0_17251__1:gpr32 = MOVi32imm 1
- ;CHECK-NEXT: %bb0_11909__2:gpr32 = LDRWui
- ;CHECK-NEXT: %bb0_44296__1:gpr32 = MOVi32imm 2
- ;CHECK-NEXT: %bb0_11909__3:gpr32 = LDRWui
- ;CHECK-NEXT: %bb0_10150__1:gpr32 = MOVi32imm 3
- ;CHECK-NEXT: %bb0_18184__1:gpr32 = nsw ADDWrr
- ;CHECK-NEXT: %bb0_11909__4:gpr32 = LDRWui
- ;CHECK-NEXT: %bb0_18184__2:gpr32 = nsw ADDWrr
- ;CHECK-NEXT: %bb0_56622__1:gpr32 = MOVi32imm 4
- ;CHECK-NEXT: %bb0_18184__3:gpr32 = nsw ADDWrr
- ;CHECK-NEXT: %bb0_11909__5:gpr32 = LDRWui
- ;CHECK-NEXT: %bb0_74788__1:gpr32 = MOVi32imm 5
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 1
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = LDRWui
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 2
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__3:gpr32 = LDRWui
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 3
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__4:gpr32 = LDRWui
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 4
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__3:gpr32 = nsw ADDWrr
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__5:gpr32 = LDRWui
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 5
%0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
%1:gpr32 = MOVi32imm 1
@@ -74,11 +74,11 @@ body: |
liveins: $x0, $x1, $d0, $d1
;CHECK-LABEL: bb.0:
- ;CHECK-NEXT: %bb0_11909__1:gpr32 = LDRWui %stack.0, 0
- ;CHECK-NEXT: %bb0_31408__1:gpr32 = COPY %bb0_11909__1
- ;CHECK-NEXT: %bb0_14282__1:gpr32 = COPY %bb0_31408__1
- ;CHECK-NEXT: %bb0_14282__2:gpr32 = COPY %bb0_14282__1
- ;CHECK-NEXT: $w0 = COPY %bb0_14282__2
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui %stack.0, 0
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1
+ ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = COPY %bb0_{{[0-9]+}}__1
+ ;CHECK-NEXT: $w0 = COPY %bb0_{{[0-9]+}}__2
%0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
%1:gpr32 = COPY %0
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
index 36d8425e7ebf..295ab75b6d82 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
@@ -1,4 +1,3 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -march=amdgcn -run-pass mir-canonicalizer %s | FileCheck %s
# This tests for the itereator invalidation fix (reviews.llvm.org/D62713)
@@ -8,18 +7,18 @@ name: foo
body: |
bb.0:
; CHECK-LABEL: name: foo
- ; CHECK: %bb0_43693__1:sreg_32_xm0 = S_MOV_B32 61440
- ; CHECK: %bb0_13829__1:sreg_32_xm0 = S_MOV_B32 0
- ; CHECK: %bb0_14481__1:vgpr_32 = COPY $vgpr0
- ; CHECK: %bb0_18142__1:sgpr_64 = COPY $sgpr0_sgpr1
- ; CHECK: %bb0_16462__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_18142__1, 9, 0, 0
- ; CHECK: %bb0_89962__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_18142__1, 11, 0, 0
- ; CHECK: %bb0_10035__1:vgpr_32 = COPY %bb0_13829__1
- ; CHECK: %bb0_18361__1:vgpr_32 = COPY %bb0_16462__1
- ; CHECK: %bb0_18361__2:vgpr_32 = COPY %bb0_89962__1
- ; CHECK: %bb0_16181__1:vreg_64 = REG_SEQUENCE %bb0_14481__1, %subreg.sub0, %bb0_10035__1, %subreg.sub1
- ; CHECK: %bb0_71315__1:sgpr_128 = REG_SEQUENCE %bb0_14481__1, %subreg.sub0, %bb0_10035__1, %subreg.sub1, %bb0_18361__1, %subreg.sub2, %bb0_18361__2, %subreg.sub3
- ; CHECK: BUFFER_STORE_DWORD_ADDR64 %bb0_10035__1, %bb0_16181__1, %bb0_71315__1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
+ ; CHECK: %bb0_{{[0-9]+}}__1:sreg_32_xm0 = S_MOV_B32 61440
+ ; CHECK: %bb0_{{[0-9]+}}__1:sreg_32_xm0 = S_MOV_B32 0
+ ; CHECK: %bb0_{{[0-9]+}}__1:vgpr_32 = COPY $vgpr0
+ ; CHECK: %bb0_{{[0-9]+}}__1:sgpr_64 = COPY $sgpr0_sgpr1
+ ; CHECK: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9]+}}__1, 9, 0, 0
+ ; CHECK: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9]+}}__1, 11, 0, 0
+ ; CHECK: %bb0_{{[0-9]+}}__1:vgpr_32 = COPY %bb0_{{[0-9]+}}__1
+ ; CHECK: %bb0_{{[0-9]+}}__1:vgpr_32 = COPY %bb0_{{[0-9]+}}__1
+ ; CHECK: %bb0_{{[0-9]+}}__2:vgpr_32 = COPY %bb0_{{[0-9]+}}__1
+ ; CHECK: %bb0_{{[0-9]+}}__1:vreg_64 = REG_SEQUENCE %bb0_{{[0-9]+}}__1, %subreg.sub0, %bb0_{{[0-9]+}}__1, %subreg.sub1
+ ; CHECK: %bb0_{{[0-9]+}}__1:sgpr_128 = REG_SEQUENCE %bb0_{{[0-9]+}}__1, %subreg.sub0, %bb0_{{[0-9]+}}__1, %subreg.sub1, %bb0_{{[0-9]+}}__1, %subreg.sub2, %bb0_{{[0-9]+}}__2, %subreg.sub3
+ ; CHECK: BUFFER_STORE_DWORD_ADDR64 %bb0_{{[0-9]+}}__1, %bb0_{{[0-9]+}}__1, %bb0_{{[0-9]+}}__1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
; CHECK: S_ENDPGM 0
%10:sreg_32_xm0 = S_MOV_B32 61440
%11:sreg_32_xm0 = S_MOV_B32 0
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