[llvm] c3607f5 - [X86][SSE] Add test for extractelement from volatile vector load

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2019-11-15T15:59:33Z
New Revision: c3607f52b1fd6fa1bbbcd34e8c593e56b721cf7a

URL: https://github.com/llvm/llvm-project/commit/c3607f52b1fd6fa1bbbcd34e8c593e56b721cf7a
DIFF: https://github.com/llvm/llvm-project/commit/c3607f52b1fd6fa1bbbcd34e8c593e56b721cf7a.diff

LOG: [X86][SSE] Add test for extractelement from volatile vector load

Mentioned in D70267

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/extractelement-load.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/extractelement-load.ll b/llvm/test/CodeGen/X86/extractelement-load.ll
index 915b9bfa8d16..9f044dc62063 100644
--- a/llvm/test/CodeGen/X86/extractelement-load.ll
+++ b/llvm/test/CodeGen/X86/extractelement-load.ll
@@ -93,3 +93,29 @@ define i64 @t4(<2 x double>* %a) {
   ret i64 %e
 }
 
+; Don't extract from a volatile.
+define void @t5(<2 x double> *%a0, double *%a1) {
+; X32-SSE2-LABEL: t5:
+; X32-SSE2:       # %bb.0:
+; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-SSE2-NEXT:    movaps (%ecx), %xmm0
+; X32-SSE2-NEXT:    movhps %xmm0, (%eax)
+; X32-SSE2-NEXT:    retl
+;
+; X64-SSSE3-LABEL: t5:
+; X64-SSSE3:       # %bb.0:
+; X64-SSSE3-NEXT:    movaps (%rdi), %xmm0
+; X64-SSSE3-NEXT:    movhps %xmm0, (%rsi)
+; X64-SSSE3-NEXT:    retq
+;
+; X64-AVX-LABEL: t5:
+; X64-AVX:       # %bb.0:
+; X64-AVX-NEXT:    vmovaps (%rdi), %xmm0
+; X64-AVX-NEXT:    vmovhps %xmm0, (%rsi)
+; X64-AVX-NEXT:    retq
+  %vecload = load volatile <2 x double>, <2 x double>* %a0, align 16
+  %vecext = extractelement <2 x double> %vecload, i32 1
+  store volatile double %vecext, double* %a1, align 8
+  ret void
+}