[llvm] dda8e95 - [MIPS GlobalISel] Select addiu
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 15 02:38:06 PST 2019
Author: Petar Avramovic
Date: 2019-11-15T11:36:13+01:00
New Revision: dda8e9554071164c85ac7b8b14bc5349703deaab
URL: https://github.com/llvm/llvm-project/commit/dda8e9554071164c85ac7b8b14bc5349703deaab
DIFF: https://github.com/llvm/llvm-project/commit/dda8e9554071164c85ac7b8b14bc5349703deaab.diff
LOG: [MIPS GlobalISel] Select addiu
Introduce IntImmLeaf version of PatLeaf immSExt16 for 32-bit immediates.
Change immSExt16 with imm32SExt16 for addiu.
This keeps same behavior for SDAG and allows for GlobalISel selectImpl
to select 'G_CONSTANT imm' + G_ADD into ADDIu when 32-bit imm satisfies
imm32SExt16 predicate: sign extending 16 low bits of imm is equal to imm.
Differential Revision: https://reviews.llvm.org/D70184
Added:
Modified:
llvm/lib/Target/Mips/MipsInstrInfo.td
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index b560da8cc717..9f07c3a914d9 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1272,6 +1272,7 @@ def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
// Node immediate fits as 16-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
+def imm32SExt16 : IntImmLeaf<i32, [{ return isInt<16>(Imm.getSExtValue()); }]>;
// Node immediate fits as 7-bit zero extended on target immediate.
def immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>;
@@ -2058,7 +2059,7 @@ def LONG_BRANCH_ADDiu2Op : PseudoSE<(outs GPR32Opnd:$dst),
/// Arithmetic Instructions (ALU Immediate)
let AdditionalPredicates = [NotInMicroMips] in {
def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
- II_ADDIU, immSExt16, add>,
+ II_ADDIU, imm32SExt16, add>,
ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1;
def ANDi : MMRel, StdMMR6Rel,
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
index a4caa06324b9..a622c581f215 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir
@@ -2,7 +2,10 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
- define void @add_i32(i32 %x, i32 %y) {entry: ret void}
+ define void @add_i32() {entry: ret void}
+ define void @add_imm() {entry: ret void}
+ define void @add_negative_imm() {entry: ret void}
+ define void @add_not_imm32SExt16() {entry: ret void}
...
---
@@ -29,3 +32,73 @@ body: |
RetRA implicit $v0
...
+---
+name: add_imm
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: add_imm
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], 3
+ ; MIPS32: $v0 = COPY [[ADDiu]]
+ ; MIPS32: RetRA implicit $v0
+ %0:gprb(s32) = COPY $a0
+ %1:gprb(s32) = G_CONSTANT i32 3
+ %2:gprb(s32) = G_ADD %0, %1
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
+---
+name: add_negative_imm
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: add_negative_imm
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], -3
+ ; MIPS32: $v0 = COPY [[ADDiu]]
+ ; MIPS32: RetRA implicit $v0
+ %0:gprb(s32) = COPY $a0
+ %1:gprb(s32) = G_CONSTANT i32 -3
+ %2:gprb(s32) = G_ADD %0, %1
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
+---
+name: add_not_imm32SExt16
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: add_not_imm32SExt16
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 65535
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[ORi]]
+ ; MIPS32: $v0 = COPY [[ADDu]]
+ ; MIPS32: RetRA implicit $v0
+ %0:gprb(s32) = COPY $a0
+ %1:gprb(s32) = G_CONSTANT i32 65535
+ %2:gprb(s32) = G_ADD %0, %1
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
index 23c4f177cfe3..31287f0d547c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
@@ -141,6 +141,40 @@ entry:
ret i128 %add
}
+define i32 @add_imm(i32 %a) {
+; MIPS32-LABEL: add_imm:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: addiu $2, $4, 3
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %add = add i32 %a, 3
+ ret i32 %add
+}
+
+define i32 @add_negative_imm(i32 %a) {
+; MIPS32-LABEL: add_negative_imm:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: addiu $2, $4, -3
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %add = add i32 %a, -3
+ ret i32 %add
+}
+
+define i32 @add_not_imm32SExt16(i32 %a) {
+; MIPS32-LABEL: add_not_imm32SExt16:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: ori $1, $zero, 65535
+; MIPS32-NEXT: addu $2, $4, $1
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %add = add i32 %a, 65535
+ ret i32 %add
+}
+
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag) {
; MIPS32-LABEL: uadd_with_overflow:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll
index 5708de834c04..fcc2d6ef0a93 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll
@@ -17,10 +17,9 @@ define void @Print_c_N_times(i8 %c, i32 %N) {
; MIPS32-NEXT: .cfi_def_cfa_register 30
; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: ori $2, $zero, 0
-; MIPS32-NEXT: addu $3, $5, $1
+; MIPS32-NEXT: addiu $3, $5, 1
; MIPS32-NEXT: mul $1, $3, $1
-; MIPS32-NEXT: ori $3, $zero, 7
-; MIPS32-NEXT: addu $1, $1, $3
+; MIPS32-NEXT: addiu $1, $1, 7
; MIPS32-NEXT: addiu $3, $zero, 65528
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: move $3, $sp
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