[PATCH] D70116: [RISCV] add subtargets initialized with target feature

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

> In addition, I think my testcase is so weird and it does not make sense there are different isa extension are used in the same compilation unit...

It's not weird, there is real use case in glibc work with IFUNC, `target` attribute for AArch64 and x86 can result different target feature in same compilation unit, and I believe such feature will implement for RISC-V in future.

  void foo(){
  }
  
  void bar() __attribute__((target("sse4")));
  void bar(){
  }


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D70116/new/

https://reviews.llvm.org/D70116