[PATCH] D70223: [DAGCombine] Split vector load-update-store into single element stores

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf updated this revision to Diff 229465.
qiucf added a comment.

- Add regression test.
- Check legality before doing costy operations.

I plan to move the two changed `swap-le` tests into another NFC patch, since they're not related to the logic. Also, currently `i8` and `i16` are illegal on PowerPC. So this won't affect vectors like `<8 x i16>` or `<16 x i8>`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70223/new/

https://reviews.llvm.org/D70223

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/swaps-le-5.ll
  llvm/test/CodeGen/PowerPC/swaps-le-6.ll
  llvm/test/CodeGen/PowerPC/vector-store-split.ll

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