[llvm] fdf1ae3 - [Hexagon] Validate the iterators before converting them to mux.

[Sumanth Gundapaneni via llvm-commits]

Author: Sumanth Gundapaneni
Date: 2019-11-14T13:01:16-06:00
New Revision: fdf1ae37cfa8718c9c4f060ad1186a57a36ca3f8

URL: https://github.com/llvm/llvm-project/commit/fdf1ae37cfa8718c9c4f060ad1186a57a36ca3f8
DIFF: https://github.com/llvm/llvm-project/commit/fdf1ae37cfa8718c9c4f060ad1186a57a36ca3f8.diff

LOG: [Hexagon] Validate the iterators before converting them to mux.

The conditional instructions that are translated to mux instructions
are deleted and the iterators to these deleted instructions are being
used later. This patch fixed this issue.

Added: 
    llvm/test/CodeGen/Hexagon/muxii-bug.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonGenMux.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
index b559e7bbbb60..9585b14dbf80 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -332,6 +332,12 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
     unsigned MxOpc = getMuxOpcode(*MX.SrcT, *MX.SrcF);
     if (!MxOpc)
       continue;
+    // Basic sanity check: since we are deleting instructions, validate the
+    // iterators. There is a possibility that one of Def1 or Def2 is translated
+    // to "mux" and being considered for other "mux" instructions.
+    if (!MX.At->getParent() || !MX.Def1->getParent() || !MX.Def2->getParent())
+      continue;
+
     MachineBasicBlock &B = *MX.At->getParent();
     const DebugLoc &DL = B.findDebugLoc(MX.At);
     auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
@@ -339,8 +345,8 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
                       .add(*MX.SrcT)
                       .add(*MX.SrcF);
     NewMux->clearKillInfo();
-    B.erase(MX.Def1);
-    B.erase(MX.Def2);
+    B.remove(MX.Def1);
+    B.remove(MX.Def2);
     Changed = true;
   }
 

diff  --git a/llvm/test/CodeGen/Hexagon/muxii-bug.ll b/llvm/test/CodeGen/Hexagon/muxii-bug.ll
new file mode 100644
index 000000000000..7267efe9e2f2
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/muxii-bug.ll
@@ -0,0 +1,30 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Make sure "generate mux" pass does not optimize out the value "1908".
+; CHECK-LABEL: foo
+; CHECK: 1908
+define internal fastcc i32 @foo(i32) #0 {
+  %2 = icmp eq i32 %0, 1
+  %3 = select i1 %2, i32 1712, i32 0
+  %4 = icmp eq i32 %0, 1
+  %5 = select i1 %4, i32 1908, i32 %3
+  %6 = icmp eq i32 %0, 1
+  %7 = icmp ult i32 %5, 1740
+  %8 = and i1 %6, %7
+  %9 = select i1 %8, i32 1740, i32 %5
+  %10 = icmp eq i32 %0, 1
+  %11 = icmp ult i32 %9, 1732
+  %12 = and i1 %10, %11
+  %13 = select i1 %12, i32 1732, i32 %9
+  %14 = icmp eq i32 %0, 2
+  %15 = icmp ult i32 %13, 1936
+  %16 = and i1 %14, %15
+  %17 = select i1 %16, i32 1936, i32 %13
+  %18 = icmp eq i32 %0, 1
+  %19 = icmp ult i32 %17, 1580
+  %20 = and i1 %18, %19
+  %21 = select i1 %20, i32 1580, i32 %17
+  ret i32 %21
+}
+
+attributes #0 = { nounwind }