[PATCH] D69891: [VP,Integer,#1] Vector-predicated integer intrinsics

[Simon Moll via Phabricator via llvm-commits]

simoll planned changes to this revision.
simoll marked 5 inline comments as done.
simoll added a comment.

- Adding scalable type example declarations
- reformatting langref for character limit.



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Comment at: llvm/docs/LangRef.rst:14668
+The explicit vector length parameter always has the type `i32`.
+The explicit vector length is only effective if the MSB of its value is zero.
+Results are only computed for enabled lanes.
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sdesmalen wrote:
> simoll wrote:
> > SjoerdMeijer wrote:
> > > Nit: instead of talking about the MSB being zero, is it simpler to say that it is effective if is a positive number (if that's what you mean)?
> > Good point. I'll rewrite that part referring to the vlen as a signed integer.
> Thanks, I wondered something similar. 
> 
> I had actually expected the `%evl` to only make sense in the context of scalable vectors?
> 
> Is it worth expressing what it means if `%evl` is larger than the size of the vector?
> I had actually expected the %evl to only make sense in the context of scalable vectors?
EVL does not require scalable vectors.  We'll use it with the `<256 x double>` type for example.


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Comment at: llvm/docs/LangRef.rst:14702
+The '``llvm.vp.add``' intrinsic performs integer addition (:ref:`add <i_add>`) of the first and second vector operand on each enabled lane.
+The result on disabled lanes is undefined.
+
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sdesmalen wrote:
> Have you considered adding an extra argument to specify the value of the false lanes, similar to how this is currently done for `llvm.masked.load`? 
> By passing `undef`, it would have similar behaviour as the current definition, yet it would remove the need to add explicit `select` statements for handling merging- or zeroing predication if an instruction supports it. For SVE for example, most instructions have either merging or zeroing predication and the intrinsics expose the merging/zeroing/undef predication directly in the C/C++ intrinsic API. I think it would be really nice to have that capability represented in the vp intrinsics as well.
Yes i considered that. However, as you suggested you can express this without loss with a  `select` and i'd like to keep the intrinsics simple.


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