[PATCH] D70176: [Codegen][ARM] Add addressing modes from masked loads and stores

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:1177
+    unsigned Ty = (unsigned)VT.SimpleTy;
+    return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf000) >> 12);
+  }
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dmgreen wrote:
> samparker wrote:
> > Is there a way that we can avoid these magic hex values?
> I'm not sure. We are trying to pull 4 bits out of an 16bit value, so the hex seems to fit perfectly!
Agreed, but how about we do that inside a few simple getter/setter helper functions? I guess that would improve readability here a bit.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70176/new/

https://reviews.llvm.org/D70176