[PATCH] D70176: [Codegen][ARM] Add addressing modes from masked loads and stores

[Dave Green via Phabricator via llvm-commits]

dmgreen marked 2 inline comments as done.
dmgreen added inline comments.


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Comment at: llvm/include/llvm/CodeGen/SelectionDAGNodes.h:2313
+  const SDValue &getOffset() const {
+    return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
+  }
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SjoerdMeijer wrote:
> This should be `ISD::MLOAD`?
Yeah. Nice spot. You can tell how many times this function gets called directly.


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Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:1177
+    unsigned Ty = (unsigned)VT.SimpleTy;
+    return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf000) >> 12);
+  }
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samparker wrote:
> Is there a way that we can avoid these magic hex values?
I'm not sure. We are trying to pull 4 bits out of an 16bit value, so the hex seems to fit perfectly!


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70176/new/

https://reviews.llvm.org/D70176