[PATCH] D70138: [TargetLowering] Increase the storage size of NumRegistersForVT to allow the type break down for v256i1 and other types to be stored correctly
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 13 12:21:12 PST 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rG84e83b54bd79: [TargetLowering] Increase the storage size of NumRegistersForVT to allow theā¦ (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70138/new/
https://reviews.llvm.org/D70138
Files:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/TargetLoweringBase.cpp
Index: llvm/lib/CodeGen/TargetLoweringBase.cpp
===================================================================
--- llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -1332,8 +1332,11 @@
MVT IntermediateVT;
MVT RegisterVT;
unsigned NumIntermediates;
- NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
+ unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
NumIntermediates, RegisterVT, this);
+ NumRegistersForVT[i] = NumRegisters;
+ assert(NumRegistersForVT[i] == NumRegisters &&
+ "NumRegistersForVT size cannot represent NumRegisters!");
RegisterTypeForVT[i] = RegisterVT;
MVT NVT = VT.getPow2VectorType();
Index: llvm/include/llvm/CodeGen/TargetLowering.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetLowering.h
+++ llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2741,7 +2741,7 @@
/// This indicates the default register class to use for each ValueType the
/// target supports natively.
const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
- unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
+ uint16_t NumRegistersForVT[MVT::LAST_VALUETYPE];
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
/// This indicates the "representative" register class to use for each
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