[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

[Victor Campos via Phabricator via llvm-commits]

vhscampos updated this revision to Diff 229043.
vhscampos added a comment.

1. Not exclude extloads anymore.
2. Create new ARMISD nodes specific to load/store of dual registers.
3. Custom lower i64 volatile loads/stores to these new ARMISD nodes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072

Files:
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/ARM/i64_volatile_load_store.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D70072.229043.patch
Type: text/x-patch
Size: 9567 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191113/1d982ee4/attachment.bin>