[PATCH] D70118: [AMDGPU] Lower llvm.amdgcn.s.buffer.load.v3[i|f]32

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D70118#1743561 <https://reviews.llvm.org/D70118#1743561>, @piotr wrote:

> Using the alignment from the ABI type alignment.
>
> The s_buffer_load intrinsic is not marked with SDNPMemOperand, so I think
>  that is why we need to create MMO here.


It probably should be marked with SDNPMemOperand, and the fact that it's IntrNoMem is another problem that should eventually be solved



================
Comment at: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll:27-31
+;GCN-LABEL: {{^}}s_buffer_load_index_divergent:
+;GCN-NOT: s_waitcnt;
+;GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
+define amdgpu_ps void @s_buffer_load_index_divergent(<4 x i32> inreg %desc, i32 %index) {
+main_body:
----------------
Most of these test changes look unrelated?


================
Comment at: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll:97-98
+;GCN-NOT: s_waitcnt;
+;GCN: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
+;GCN: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
+define amdgpu_ps void @s_buffer_loadx3_index(<4 x i32> inreg %desc, i32 inreg %index) {
----------------
There is no load dwordx3, so I'm slightly confused about why you need this, but I would expect this ot widen to 4x loads?


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  https://reviews.llvm.org/D70118/new/

https://reviews.llvm.org/D70118