[PATCH] D70082: [AArch64] Extend storeRegToStackSlot to spill SVE registers.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Thanks for the review!



================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:3048
+    StackID = TargetStackID::SVEVector;
+  } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
+    assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
----------------
efriedma wrote:
> We'll eventually need to handle ZPR2 etc.?  I guess we don't need that immediately.
Correct! We can implement this with Pseudos that expand to individual LDR_ZXI/STR_ZXI instructions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70082/new/

https://reviews.llvm.org/D70082