[llvm] 98856e3 - [AArch64] Fix addressing mode predicates
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 12 12:40:04 PST 2019
Author: Evandro Menezes
Date: 2019-11-12T14:37:28-06:00
New Revision: 98856e3943de698f8c1d940c08bdbf50f04937b4
URL: https://github.com/llvm/llvm-project/commit/98856e3943de698f8c1d940c08bdbf50f04937b4
DIFF: https://github.com/llvm/llvm-project/commit/98856e3943de698f8c1d940c08bdbf50f04937b4.diff
LOG: [AArch64] Fix addressing mode predicates
Fix predicates related to the register offset addressing mode.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SchedPredicates.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
index e155652318ab..028ad2232c9b 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -41,7 +41,7 @@ let FunctionMapper = "AArch64_AM::getMemExtendType" in {
// Check for scaling in the register offset addressing mode.
let FunctionMapper = "AArch64_AM::getMemDoShift" in
-def CheckMemScaled : CheckImmOperandSimple<3>;
+def CheckMemScaled : CheckImmOperandSimple<4>;
// Check the shifting type in arithmetic and logic instructions.
let FunctionMapper = "AArch64_AM::getShiftType" in {
@@ -319,7 +319,8 @@ def IsLoadRegOffsetOp : CheckOpcode<[PRFMroW, PRFMroX,
LDRBroW, LDRBroX,
LDRHroW, LDRHroX,
LDRSroW, LDRSroX,
- LDRDroW, LDRDroX]>;
+ LDRDroW, LDRDroX,
+ LDRQroW, LDRQroX]>;
// Identify whether an instruction is a load
// using the register offset addressing mode.
@@ -330,7 +331,8 @@ def IsStoreRegOffsetOp : CheckOpcode<[STRBBroW, STRBBroX,
STRBroW, STRBroX,
STRHroW, STRHroX,
STRSroW, STRSroX,
- STRDroW, STRDroX]>;
+ STRDroW, STRDroX,
+ STRQroW, STRQroX]>;
// Identify whether an instruction is a load or
// store using the register offset addressing mode.
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