[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

We have started tallying the instructions against the spec. So far we have found the following missing instructions:

- `vdot.vv` / `vdotu.vv` / `vfdot.vv`



================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1418
+  Encoding = (sew.logBase2() << 2) | lmul.logBase2();
+  Operands.push_back(RISCVOperand::createVType(sew.logBase2(), lmul.logBase2(),
+                                               S, Encoding, isRV64()));
----------------
Could this encoding logic be in `RISCVOperand::createVType` itself?

You would have to pass `sew` and `lmul` without doing `logBase2()` here and the call in line `1395` would set `lmul = 1`.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:238
+// Vector registers
+let RegAltNameIndices = [ABIRegAltName] in {
+  def V0  : RISCVReg<0, "v0", ["v0"]>, DwarfRegNum<[64]>;
----------------
Would it help to simplify this as

```
// Define V0-V31
let RegAltNameIndices = [ABIRegAltName] in {
   foreach Index = 0-31 in {
      def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>,
       DwarfRegNum<[!add(#Index, 64)]>;
   }
}
```


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:281
+// meaning caller-save regs are listed before callee-save.
+def VPR : RegisterClass<"RISCV", VLenVT.types,
+                        128, (add
----------------
What does the `P` in `VPR` stand for?


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