[PATCH] D70124: [RISCV] Use addi rather than add x0

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
lenary added a reviewer: luismarques.
Herald added subscribers: llvm-commits, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, asb, hiraditya.
Herald added a project: LLVM.

The RISC-V backend used to generate `add <reg>, x0, <reg>` in a few
instances. It seems most places no longer generate this sequence.

This is semantically equivalent to `addi <reg>, <reg>, 0`, but the
latter has the advantage of being noted to be the canonical instruction
to be used for moves (which microarchitectures can and should recognise
as such).

The changed testcases use instruction aliases - `mv <reg>, <reg>` is an
alias for `addi <reg>, <reg>, 0`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70124

Files:
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/test/CodeGen/RISCV/atomic-rmw.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D70124.228893.patch
Type: text/x-patch
Size: 7262 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191112/f313bbce/attachment.bin>