[PATCH] D70124: [RISCV] Use addi rather than add x0
Sam Elliott via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 12 07:31:55 PST 2019
lenary created this revision.
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The RISC-V backend used to generate `add <reg>, x0, <reg>` in a few
instances. It seems most places no longer generate this sequence.
This is semantically equivalent to `addi <reg>, <reg>, 0`, but the
latter has the advantage of being noted to be the canonical instruction
to be used for moves (which microarchitectures can and should recognise
as such).
The changed testcases use instruction aliases - `mv <reg>, <reg>` is an
alias for `addi <reg>, <reg>, 0`.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D70124
Files:
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
llvm/test/CodeGen/RISCV/atomic-rmw.ll
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