[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Hi @HsiangKai,

It may be possible to halve the number of instructions if we make use of the `IsOptional` attribute and we always add a //mask// operand to the instructions that may have a mask. This way we don't have `VADD_VV` and `VADD_VV_T`, only `VADD_VV` with a mask operand whose register is `RISCV::NoRegister` if the instruction is not masked.

You can find a PoC at D70092 <https://reviews.llvm.org/D70092>.

Perhaps you already considered this approach and discarded it?

What do you think?


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  rL LLVM

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https://reviews.llvm.org/D69987