[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang marked an inline comment as done.
steven.zhang added inline comments.


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Comment at: llvm/test/CodeGen/ARM/signext-inreg.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=armv8 -mattr=+mve | FileCheck %s
 define <4 x i32> @test(<4 x i32> %m) {
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dmgreen wrote:
> There are already tests in Thumb2/mve-sext.ll which cover sexts. The target here is a little odd for mve (mixing A profile and M profile architectures).
I am not familiar with Arm target... From the implementation, it is valid case to show the issue. I will take a look at the case you mentioned. Thank you!


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