[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

It seems that this thing has been around since 2010. How come we are changing the default now, as opposed to just fixing the backends that don't support this instruction?

If MIPs is the target that is failing, there should probably be a test to show it is now OK.



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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:368
 
+  // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8,  Legal);
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Nice one.


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Comment at: llvm/test/CodeGen/ARM/signext-inreg.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=armv8 -mattr=+mve | FileCheck %s
 define <4 x i32> @test(<4 x i32> %m) {
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There are already tests in Thumb2/mve-sext.ll which cover sexts. The target here is a little odd for mve (mixing A profile and M profile architectures).


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  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000