[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added a comment.

- llvm/test/CodeGen/ARM/signext-inreg.ll Expose a bug. Because the default action is legal, we have to set it as expand inside addTypeForNEON. And it will override the action set for MVE.  Change it to expand by default, and set it to legal for MVE.
- CodeGen/Hexagon/signext-inreg.ll Without this patch, we fail to select the instruction for test3 with option -march=hexagon. This is because all the sext_inreg for the vector type is legal by default if the target didn't set it. And Hexagon is the target. It will generate the sext_inreg node that target didn't support, which hit the assertion in the instruction selection. And this is exactly the case that this patch want to avoid.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000