[PATCH] D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics.

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr added a comment.

@sdesmalen, would you have any objections if I implemented it as @efriedma suggested?

In D69956#1737938 <https://reviews.llvm.org/D69956#1737938>, @efriedma wrote:

> For the FPR8 thing, we've run into it before; see https://reviews.llvm.org/D46851 .  We should probably look into adding i8 to FPR8; not sure how hard it is, but it makes sense semantically.
>
> We could select these for llvm.experimental.vector.reduce.*, but that doesn't seem like it's high-priority.
>
> LGTM


I think that implementing that way would make it simpler for implementing other patterns that have i8 and i16 outputs in the future.


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