[PATCH] D70042: [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4)

[Joan LLuch via Phabricator via llvm-commits]

joanlluch marked an inline comment as done.
joanlluch added inline comments.


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Comment at: llvm/lib/Target/MSP430/MSP430ISelLowering.cpp:364
+                                                       unsigned amount) const {
+  return !(amount == 8 || amount == 9 || amount<=2);
 }
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spatel wrote:
> This changes the MSP430 output for shift by 8 or 9? If yes, there should be tests that show this difference.
I commited baseline tests to show this (D70083). I did not wait for review in this particular case, as I understand it's simple enough. (It does not modify any code) (I hope this is ok). 
I will submit an updated patch for this.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D70042/new/

https://reviews.llvm.org/D70042