[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

[Victor Campos via Phabricator via llvm-commits]

vhscampos created this revision.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls.
Herald added a project: LLVM.

Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now emit a single LDRD or STRD.

These improvements cover architectures implementing ARMv5TE or Thumb-2.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70072

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/ARM/i64_volatile_load_store.ll

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