[PATCH] D66088: AMD Znver2 (Rome) Scheduler enablement

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

Not sure how this (any) sched model should be reviewed.
Perhaps it would help to post the exegesis reports.

FWIW i'd just merge this.



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Comment at: llvm/lib/Target/X86/X86ScheduleZnver2.td:179
+def : WriteRes<WriteMove,    [Zn2ALU]>;
+def : WriteRes<WriteLoad,    [Zn2AGU]> { let Latency = 8; }
+
----------------
This is correct?
Shouldn't it be 4+1 ?


Repository:
  rL LLVM

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  https://reviews.llvm.org/D66088/new/

https://reviews.llvm.org/D66088