[PATCH] D69601: [Power9] Implement the vector extend sign instruction pattern match

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:4305
 
+  let Predicates = [HasP9Altivec] in {
+    def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i8)), (v4i32 (VEXTSB2W $VRB))>;
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I don't really see a reason to put this into PPCInstrVSX.td. Seems like PPCInstrAltivec.td would be a more appropriate place for it.


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  https://reviews.llvm.org/D69601/new/

https://reviews.llvm.org/D69601