[PATCH] D70029: [MIR-Renamer][WIP] opcode-chain based Canonical MIR VReg renaming.

[Puyan Lotfi via Phabricator via llvm-commits]

plotfi created this revision.
plotfi added a reviewer: aditya_nandakumar.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

This patch is a first stab at renaming vregs not by an index increment but by the chain of encountered instruction opcodes in the defuse. Ideally something like:

  %36:fpr64 = LDRDroX killed %30, %35, 0, 0
  %38:gpr32common = ADDWri %32, 20, 0
  %39:gpr64common = SMADDLrrr killed %38, %24, killed %37
  STRDroX killed %36, killed %39, %35, 0, 0

Can be renamed to:

  %STRDroXSBFMXr35:gpr64 = SBFMXri %STRDroXINSERT_SUBRE39, 61, 31
  %STRDroXLDRDro33:fpr64 = LDRDroX %STRDroXLDRXu36, %STRDroXSBFMXr35, 0, 0
  %STRDroXSMADDLrr34:gpr64common = SMADDLrrr %STRDroXADDWr37, %STURDiMOVi32im30, %STRDroXLDRXu38
  STRDroX %STRDroXLDRDro33, %STRDroXSMADDLrr34, %BSTRDroXSBFMXr35, 0, 0

This is a rough work in progress. Only posting something this early without tests so that others can mess with it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70029

Files:
  llvm/lib/CodeGen/MIRNamerPass.cpp
  llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
  llvm/lib/CodeGen/MIRVRegNamerUtils.h

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