[PATCH] D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Thanks for this patch @dancgr!

I'd suggest already doing the extra work to support i8 and i16 in this patch, so that the same mechanism can be used for all the i8, i16, i32 and i64 patterns.

One way to do this would be to lower the intrinsics to a custom AArch64ISD node that returns a fixed-width vector (e.g. `AArch64::UMAXV_PRED`), from which element 0 can be extracted.
For example:

  def SDT_AArch64Reduce : SDTypeProfile<1, 2, [SDTCisVec<1>, SDTCisVec<2>]>;
  def AArch64umaxv_pred   : SDNode<"AArch64ISD::UMAXV_PRED",   SDT_AArch64Reduce>;

The pattern would then insert its result into a wider vector:

  def : Pat<(v16i8 (op (nxv16i1 PPR3bAny:$Pg), (nxv16i8 ZPR8:$Zn))),
            (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast<Instruction>(NAME#_B) PPR3bAny:$Pg, ZPR8:$Zn), bsub)>;

This only requires a simple combine rule in ISelLowering that transforms the umaxv intrinsic into the `UMAXV_PRED` and adds the `EXTRACT_ELEMENT` operation to extract the byte value from element 0.



================
Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:832
+class AdvSIMD_SVE_Int_Reduce_Intrinsic
+  : Intrinsic<[llvm_anyint_ty],
+              [LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>,
----------------
The result type should rather be `LLVMVectorElementType<0>` instead of `llvm_anyint_ty`.


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