[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:699
+    }
+  }
+
----------------
Indention seems weird for getSEWStr and getLMULStr?


================
Comment at: llvm/test/MC/RISCV/rvv/vsetvl.s:9
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vsetvli a2, a0, e32,m4
+// CHECK-INST: vsetvli a2, a0, e32,m4
----------------
Add a testcase for `vsetvli a2, a0, e32`, spec say LMUL can be omitted and default to m1[1], and need negative testcase would be better, e.g. feed `e31` and `m3`.

[1] https://riscv.github.io/documents/riscv-v-spec/#_vsetvlivsetvl_instructions


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69987/new/

https://reviews.llvm.org/D69987