[PATCH] D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

For the FPR8 thing, we've run into it before; see https://reviews.llvm.org/D46851 .  We should probably look into adding i8 to FPR8; not sure how hard it is, but it makes sense semantically.

We could select these for llvm.experimental.vector.reduce.*, but that doesn't seem like it's high-priority.

LGTM



================
Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:843
+
+class AdvSIMD_Pred1VectorArg_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
----------------
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