[PATCH] D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description.

James Y Knight via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 7 08:46:16 PST 2019


jyknight added a comment.

In D64830#1736412 <https://reviews.llvm.org/D64830#1736412>, @andreisfr wrote:

> @jyknight , as I'm understood, Cadence doesn;t want to publish Xtensa ISA. But it seems that documentation from the link that you provided is quite actual, probably it was published when Xtensa was owned by Tensilica. Also, the code can be reviewed by people from companies that use Xtensa IP in their chips.


That seems really silly -- why wouldn't someone want all users of their CPUs to be able to easily access the ISA docs. Oh well.

Anyways, are there some folks who know LLVM and do have access to the official documentation who can help review the patches? (Maybe asking on the mailing list thread would be useful.)

> BTW there is also an ARC backend (from Synopsys), and I have not found any public documentation with ARC ISA, so probably encoding of ARC instructions also could be verified only by Synopsys engineers.
> 
> Also we could prepare summary about Xtensa ISA based on public resources like GCC, Binutils, QEMU with quality enough for code review. What do you think?

I think a short summary of the general characteristics of the CPU/ISA would be useful. I do not think that it would be a productive use of time to attempt to reverse-engineer/rewrite an entire ISA doc -- having such a reverse-engineered and possibly incorrect or outdated doc might even be worse than not having it. But I do not think lack of public documentation should be a blocker for inclusion, especially if there are folks who do have access to the privately-available documentation who can help review.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64830/new/

https://reviews.llvm.org/D64830





More information about the llvm-commits mailing list