[PATCH] D69919: [AMDGPU] Add handling of 160 bit registers in analyzeResourceUsage

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 228160.
rampitec added a comment.

Added test.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69919/new/

https://reviews.llvm.org/D69919

Files:
  llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll


Index: llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
+++ llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
@@ -238,6 +238,34 @@
   ret void
 }
 
+; Make sure there's no assert when a sgpr160 is used.
+; GCN-LABEL: {{^}}count_use_sgpr160_external_call
+; GCN: ; sgpr160 s[{{[0-9]+}}:{{[0-9]+}}]
+; CI: NumSgprs: 48
+; VI-NOBUG: NumSgprs: 48
+; VI-BUG: NumSgprs: 96
+; GCN: NumVgprs: 24
+define amdgpu_kernel void @count_use_sgpr160_external_call()  {
+entry:
+  tail call void asm sideeffect "; sgpr160 $0", "s"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
+  call void @external()
+  ret void
+}
+
+; Make sure there's no assert when a vgpr160 is used.
+; GCN-LABEL: {{^}}count_use_vgpr160_external_call
+; GCN: ; vgpr160 v[{{[0-9]+}}:{{[0-9]+}}]
+; CI: NumSgprs: 48
+; VI-NOBUG: NumSgprs: 48
+; VI-BUG: NumSgprs: 96
+; GCN: NumVgprs: 24
+define amdgpu_kernel void @count_use_vgpr160_external_call()  {
+entry:
+  tail call void asm sideeffect "; vgpr160 $0", "v"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
+  call void @external()
+  ret void
+}
+
 attributes #0 = { nounwind noinline norecurse }
 attributes #1 = { nounwind noinline norecurse }
 attributes #2 = { nounwind noinline }
Index: llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -793,6 +793,7 @@
           IsSGPR = false;
           Width = 3;
         } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
+          IsSGPR = true;
           Width = 3;
         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
@@ -806,6 +807,12 @@
           IsSGPR = false;
           IsAGPR = true;
           Width = 4;
+        } else if (AMDGPU::VReg_160RegClass.contains(Reg)) {
+          IsSGPR = false;
+          Width = 5;
+        } else if (AMDGPU::SReg_160RegClass.contains(Reg)) {
+          IsSGPR = true;
+          Width = 5;
         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
             "trap handler registers should not be used");


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