[PATCH] D69891: [VP,Integer,#1] Vector-predicated integer intrinsics

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


================
Comment at: llvm/lib/IR/IntrinsicInst.cpp:216
+
+bool VPIntrinsic::canIgnoreVectorLengthParam() const {
+  auto StaticVL = getStaticVectorLength();
----------------
Are you flexible on this..? For Arm's MVE, it would be useful for us to be able to use a vector length even though we have a fixed vector width. We are trying to use the vectorizers tail folding ability and it could be really nice to use the vector length instead of performing a vector icmp for active lanes. This could free up the 'mask' for other conditions within the loop without having to compare conditions (which will be expensive for us).


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https://reviews.llvm.org/D69891