[llvm] 3ce0c78 - [InstCombine] add tests for shift-logic-shift; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 5 05:51:28 PST 2019
Author: Sanjay Patel
Date: 2019-11-05T08:18:50-05:00
New Revision: 3ce0c78501813e7a278573d78a0be47755ed0518
URL: https://github.com/llvm/llvm-project/commit/3ce0c78501813e7a278573d78a0be47755ed0518
DIFF: https://github.com/llvm/llvm-project/commit/3ce0c78501813e7a278573d78a0be47755ed0518.diff
LOG: [InstCombine] add tests for shift-logic-shift; NFC
This is based on existing CodeGen test files for x86 and AArch64.
The corresponding potential transform is shown in:
rL370617
Added:
llvm/test/Transforms/InstCombine/shift-logic.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/shift-logic.ll b/llvm/test/Transforms/InstCombine/shift-logic.ll
new file mode 100644
index 000000000000..f387d1f738be
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/shift-logic.ll
@@ -0,0 +1,171 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i8 @shl_and(i8 %x, i8 %y) {
+; CHECK-LABEL: @shl_and(
+; CHECK-NEXT: [[SH0:%.*]] = shl i8 [[X:%.*]], 3
+; CHECK-NEXT: [[R:%.*]] = and i8 [[SH0]], [[Y:%.*]]
+; CHECK-NEXT: [[SH1:%.*]] = shl i8 [[R]], 2
+; CHECK-NEXT: ret i8 [[SH1]]
+;
+ %sh0 = shl i8 %x, 3
+ %r = and i8 %sh0, %y
+ %sh1 = shl i8 %r, 2
+ ret i8 %sh1
+}
+
+define i16 @shl_or(i16 %x, i16 %py) {
+; CHECK-LABEL: @shl_or(
+; CHECK-NEXT: [[Y:%.*]] = srem i16 [[PY:%.*]], 42
+; CHECK-NEXT: [[SH0:%.*]] = shl i16 [[X:%.*]], 5
+; CHECK-NEXT: [[R:%.*]] = or i16 [[Y]], [[SH0]]
+; CHECK-NEXT: [[SH1:%.*]] = shl i16 [[R]], 7
+; CHECK-NEXT: ret i16 [[SH1]]
+;
+ %y = srem i16 %py, 42 ; thwart complexity-based canonicalization
+ %sh0 = shl i16 %x, 5
+ %r = or i16 %y, %sh0
+ %sh1 = shl i16 %r, 7
+ ret i16 %sh1
+}
+
+define i32 @shl_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @shl_xor(
+; CHECK-NEXT: [[SH0:%.*]] = shl i32 [[X:%.*]], 5
+; CHECK-NEXT: [[R:%.*]] = xor i32 [[SH0]], [[Y:%.*]]
+; CHECK-NEXT: [[SH1:%.*]] = shl i32 [[R]], 7
+; CHECK-NEXT: ret i32 [[SH1]]
+;
+ %sh0 = shl i32 %x, 5
+ %r = xor i32 %sh0, %y
+ %sh1 = shl i32 %r, 7
+ ret i32 %sh1
+}
+
+define i64 @lshr_and(i64 %x, i64 %py) {
+; CHECK-LABEL: @lshr_and(
+; CHECK-NEXT: [[Y:%.*]] = srem i64 [[PY:%.*]], 42
+; CHECK-NEXT: [[SH0:%.*]] = lshr i64 [[X:%.*]], 5
+; CHECK-NEXT: [[R:%.*]] = and i64 [[Y]], [[SH0]]
+; CHECK-NEXT: [[SH1:%.*]] = lshr i64 [[R]], 7
+; CHECK-NEXT: ret i64 [[SH1]]
+;
+ %y = srem i64 %py, 42 ; thwart complexity-based canonicalization
+ %sh0 = lshr i64 %x, 5
+ %r = and i64 %y, %sh0
+ %sh1 = lshr i64 %r, 7
+ ret i64 %sh1
+}
+
+define <4 x i32> @lshr_or(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @lshr_or(
+; CHECK-NEXT: [[SH0:%.*]] = lshr <4 x i32> [[X:%.*]], <i32 5, i32 5, i32 5, i32 5>
+; CHECK-NEXT: [[R:%.*]] = or <4 x i32> [[SH0]], [[Y:%.*]]
+; CHECK-NEXT: [[SH1:%.*]] = lshr <4 x i32> [[R]], <i32 7, i32 7, i32 7, i32 7>
+; CHECK-NEXT: ret <4 x i32> [[SH1]]
+;
+ %sh0 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
+ %r = or <4 x i32> %sh0, %y
+ %sh1 = lshr <4 x i32> %r, <i32 7, i32 7, i32 7, i32 7>
+ ret <4 x i32> %sh1
+}
+
+define <8 x i16> @lshr_xor(<8 x i16> %x, <8 x i16> %py) {
+; CHECK-LABEL: @lshr_xor(
+; CHECK-NEXT: [[Y:%.*]] = srem <8 x i16> [[PY:%.*]], <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
+; CHECK-NEXT: [[SH0:%.*]] = lshr <8 x i16> [[X:%.*]], <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+; CHECK-NEXT: [[R:%.*]] = xor <8 x i16> [[Y]], [[SH0]]
+; CHECK-NEXT: [[SH1:%.*]] = lshr <8 x i16> [[R]], <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+; CHECK-NEXT: ret <8 x i16> [[SH1]]
+;
+ %y = srem <8 x i16> %py, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 -42> ; thwart complexity-based canonicalization
+ %sh0 = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
+ %r = xor <8 x i16> %y, %sh0
+ %sh1 = lshr <8 x i16> %r, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+ ret <8 x i16> %sh1
+}
+
+
+define <16 x i8> @ashr_and(<16 x i8> %x, <16 x i8> %py, <16 x i8> %pz) {
+; CHECK-LABEL: @ashr_and(
+; CHECK-NEXT: [[Y:%.*]] = srem <16 x i8> [[PY:%.*]], [[PZ:%.*]]
+; CHECK-NEXT: [[SH0:%.*]] = ashr <16 x i8> [[X:%.*]], <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; CHECK-NEXT: [[R:%.*]] = and <16 x i8> [[Y]], [[SH0]]
+; CHECK-NEXT: [[SH1:%.*]] = ashr <16 x i8> [[R]], <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+; CHECK-NEXT: ret <16 x i8> [[SH1]]
+;
+ %y = srem <16 x i8> %py, %pz ; thwart complexity-based canonicalization
+ %sh0 = ashr <16 x i8> %x, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+ %r = and <16 x i8> %y, %sh0
+ %sh1 = ashr <16 x i8> %r, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
+ ret <16 x i8> %sh1
+}
+
+define <2 x i64> @ashr_or(<2 x i64> %x, <2 x i64> %y) {
+; CHECK-LABEL: @ashr_or(
+; CHECK-NEXT: [[SH0:%.*]] = ashr <2 x i64> [[X:%.*]], <i64 5, i64 5>
+; CHECK-NEXT: [[R:%.*]] = or <2 x i64> [[SH0]], [[Y:%.*]]
+; CHECK-NEXT: [[SH1:%.*]] = ashr <2 x i64> [[R]], <i64 7, i64 7>
+; CHECK-NEXT: ret <2 x i64> [[SH1]]
+;
+ %sh0 = ashr <2 x i64> %x, <i64 5, i64 5>
+ %r = or <2 x i64> %sh0, %y
+ %sh1 = ashr <2 x i64> %r, <i64 7, i64 7>
+ ret <2 x i64> %sh1
+}
+
+define i32 @ashr_xor(i32 %x, i32 %py) {
+; CHECK-LABEL: @ashr_xor(
+; CHECK-NEXT: [[Y:%.*]] = srem i32 [[PY:%.*]], 42
+; CHECK-NEXT: [[SH0:%.*]] = ashr i32 [[X:%.*]], 5
+; CHECK-NEXT: [[R:%.*]] = xor i32 [[Y]], [[SH0]]
+; CHECK-NEXT: [[SH1:%.*]] = ashr i32 [[R]], 7
+; CHECK-NEXT: ret i32 [[SH1]]
+;
+ %y = srem i32 %py, 42 ; thwart complexity-based canonicalization
+ %sh0 = ashr i32 %x, 5
+ %r = xor i32 %y, %sh0
+ %sh1 = ashr i32 %r, 7
+ ret i32 %sh1
+}
+
+define i32 @shr_mismatch_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @shr_mismatch_xor(
+; CHECK-NEXT: [[SH0:%.*]] = ashr i32 [[X:%.*]], 5
+; CHECK-NEXT: [[R:%.*]] = xor i32 [[SH0]], [[Y:%.*]]
+; CHECK-NEXT: [[SH1:%.*]] = lshr i32 [[R]], 7
+; CHECK-NEXT: ret i32 [[SH1]]
+;
+ %sh0 = ashr i32 %x, 5
+ %r = xor i32 %y, %sh0
+ %sh1 = lshr i32 %r, 7
+ ret i32 %sh1
+}
+
+define i32 @ashr_overshift_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_overshift_xor(
+; CHECK-NEXT: [[SH0:%.*]] = ashr i32 [[X:%.*]], 15
+; CHECK-NEXT: [[R:%.*]] = xor i32 [[SH0]], [[Y:%.*]]
+; CHECK-NEXT: [[SH1:%.*]] = ashr i32 [[R]], 17
+; CHECK-NEXT: ret i32 [[SH1]]
+;
+ %sh0 = ashr i32 %x, 15
+ %r = xor i32 %y, %sh0
+ %sh1 = ashr i32 %r, 17
+ ret i32 %sh1
+}
+
+define i32 @lshr_or_extra_use(i32 %x, i32 %y, i32* %p) {
+; CHECK-LABEL: @lshr_or_extra_use(
+; CHECK-NEXT: [[SH0:%.*]] = lshr i32 [[X:%.*]], 5
+; CHECK-NEXT: [[R:%.*]] = or i32 [[SH0]], [[Y:%.*]]
+; CHECK-NEXT: store i32 [[R]], i32* [[P:%.*]], align 4
+; CHECK-NEXT: [[SH1:%.*]] = lshr i32 [[R]], 7
+; CHECK-NEXT: ret i32 [[SH1]]
+;
+ %sh0 = lshr i32 %x, 5
+ %r = or i32 %sh0, %y
+ store i32 %r, i32* %p
+ %sh1 = lshr i32 %r, 7
+ ret i32 %sh1
+}
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