[llvm] 4cbe10e - [AArch64] Update for Exynos

[Evandro Menezes via llvm-commits]

Author: Evandro Menezes
Date: 2019-11-04T16:21:28-06:00
New Revision: 4cbe10efc2011641f72357685feff35ca87ed0d5

URL: https://github.com/llvm/llvm-project/commit/4cbe10efc2011641f72357685feff35ca87ed0d5
DIFF: https://github.com/llvm/llvm-project/commit/4cbe10efc2011641f72357685feff35ca87ed0d5.diff

LOG: [AArch64] Update for Exynos

Fix the costs of integer division.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SchedExynosM4.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
index 447cdee1679f..60a6a2bbd5f8 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
@@ -175,8 +175,10 @@ def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
                                            let ResourceCycles = [2]; }
 
-def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12; }
-def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21; }
+def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12;
+                                            let ResourceCycles = [12]; }
+def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21;
+                                            let ResourceCycles = [21]; }
 
 def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }