[llvm] 4531aee - [amdgpu] Fix known bits compuation on `MUL_I24`/`MUL_U24`.

[Michael Liao via llvm-commits]

Author: Michael Liao
Date: 2019-11-01T17:06:17-04:00
New Revision: 4531aee2ac1609e8ddf4f3deec200c5f793faa7b

URL: https://github.com/llvm/llvm-project/commit/4531aee2ac1609e8ddf4f3deec200c5f793faa7b
DIFF: https://github.com/llvm/llvm-project/commit/4531aee2ac1609e8ddf4f3deec200c5f793faa7b.diff

LOG: [amdgpu] Fix known bits compuation on `MUL_I24`/`MUL_U24`.

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, dstuttard, tpr, t-tye, hiraditya, llvm-commits, yaxunl

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69735

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 1115d8c23620..8912ef446034 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4435,6 +4435,9 @@ void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
     unsigned TrailZ = LHSKnown.countMinTrailingZeros() +
                       RHSKnown.countMinTrailingZeros();
     Known.Zero.setLowBits(std::min(TrailZ, 32u));
+    // Skip extra check if all bits are known zeros.
+    if (TrailZ >= 32)
+      break;
 
     // Truncate to 24 bits.
     LHSKnown = LHSKnown.trunc(24);

diff  --git a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
index 125f76ae10ed..6f3659cbd94d 100644
--- a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
@@ -157,3 +157,14 @@ define i32 @num_sign_bits_mul_i32_10(i32 %x, i32 %y, i32 %z, i32 %w) {
   %mul2 = mul i32 %mul0, %mul1
   ret i32 %mul2
 }
+
+; GFX9-LABEL: known_bits_mul24:
+; GFX9: v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    s_setpc_b64
+define i32 @known_bits_mul24() {
+  %r0 = call i32 @llvm.amdgcn.mul.i24(i32 0, i32 -7)
+  %r1 = shl i32 %r0, 2
+  ret i32 %r1
+}
+
+declare i32 @llvm.amdgcn.mul.i24(i32, i32)