[PATCH] D69545: [globalisel][docs] Rework GMIR documentation and add an early GenericOpcode reference

[Diana Picus via Phabricator via llvm-commits]

rovka added a comment.

Just a few more typos and stuff.



================
Comment at: llvm/docs/GlobalISel/GMIR.rst:93
+just physically stored apart and each instruction can only access registers from
+A or register B but never a mix of the two. If we want to perform an operation
+on data that's in split between the two register files, we must first copy all
----------------
Typo "or register B"


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:98
+
+Sign extend the a value from an arbitrary bit position, copying the sign bit
+into all bits above it. This is equivalent to a shl + ashr pair with an
----------------
Typo: "the a value"


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:206
+
+Extract multiple registers specified size, starting from blocks given by
+indexes. This will almost certainly be mapped to sub-register COPYs after
----------------
Typo: "multiple registers specified size"


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:219
+
+Reverse the order of the bytes in a scalar
+
----------------
Punctuation.


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:228
+
+Reverse the order of the bits in a scalar
+
----------------
Ditto.


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:269
+
+Add an offset to a pointer.
+
----------------
I think it's ok for some of the other instructions to have a more summary description and no code block at the moment, but it would be nice to brush this one up a bit since it's different from what people might expect.


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:273
+
+  This instruction is misleadingly named. It bears little resemblence to
+  :ref:`i_getelementptr`.
----------------
I'm not a native speaker but I think it's resembl**a**nce.


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:312
+
+  %3:_(s32), %4:_(s1) = G_UADDO %0, %1
+
----------------
Code block should use G_UADDE


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:318
+Multiply two numbers at twice the incoming bit width (signed) and return
+the high half of the result
+
----------------
Missing punctuation.


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:322
+
+  %3:_(s32), %4:_(s1) = G_UADDO %0, %1
+
----------------
Code block should use G_UMULH


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:327
+
+Count leading zeros, trailing zeros, or number of set bits
+
----------------
Missing punctuation and code block.


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:348
+
+Floating point negation
+
----------------
Missing punctuation for this and the following ones.


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:418
+
+NaN-propagating minimum that also treat -0.0 as less than 0.0. While
+FMINNUM_IEEE follow IEEE 754-2008 semantics, FMINIMUM follows IEEE 754-2018
----------------
Typo: treat


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:437
+
+Perform a fused multiple add (i.e. without the intermediate rounding step).
+
----------------
Typo: "fused multiple add"


================
Comment at: llvm/docs/GlobalISel/GenericOpcode.rst:442
+
+Perform a non-fused multiple add (i.e. with the intermediate rounding step).
+
----------------
Ditto.


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