[llvm] edca9ac - AMDGPU: Don't fold S_NOPs with implicit operands

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2019-10-30T14:40:56-07:00
New Revision: edca9ac0de3a5c10a21ef0c725501ea35791006a

URL: https://github.com/llvm/llvm-project/commit/edca9ac0de3a5c10a21ef0c725501ea35791006a
DIFF: https://github.com/llvm/llvm-project/commit/edca9ac0de3a5c10a21ef0c725501ea35791006a.diff

LOG: AMDGPU: Don't fold S_NOPs with implicit operands

Added: 
    llvm/test/CodeGen/AMDGPU/nop-fold.mir

Modified: 
    llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 8afca2cdc325..3986ca6dfa81 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -603,8 +603,10 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
       //  =>
       // s_nop (N + M)
       if (MI.getOpcode() == AMDGPU::S_NOP &&
+          MI.getNumOperands() == 1 && // Don't merge with implicit operands
           Next != MBB.end() &&
-          (*Next).getOpcode() == AMDGPU::S_NOP) {
+          (*Next).getOpcode() == AMDGPU::S_NOP &&
+          (*Next).getNumOperands() == 1) {
 
         MachineInstr &NextMI = *Next;
         // The instruction encodes the amount to wait with an offset of 1,

diff  --git a/llvm/test/CodeGen/AMDGPU/nop-fold.mir b/llvm/test/CodeGen/AMDGPU/nop-fold.mir
new file mode 100644
index 000000000000..e014f321280a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/nop-fold.mir
@@ -0,0 +1,137 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -run-pass=si-shrink-instructions %s -o - | FileCheck %s
+
+---
+
+name:            merge_2_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_2_nop
+    ; CHECK: S_NOP 1
+    S_NOP 0
+    S_NOP 0
+
+...
+
+---
+
+name:            merge_3_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_3_nop
+    ; CHECK: S_NOP 2
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+
+
+...
+
+---
+
+name:            merge_7_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_7_nop
+    ; CHECK: S_NOP 6
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+
+...
+
+---
+
+name:            merge_8_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_8_nop
+    ; CHECK: S_NOP 7
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+
+...
+---
+
+name:            merge_9_nop
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: merge_9_nop
+    ; CHECK: S_NOP 7
+    ; CHECK: S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+    S_NOP 0
+
+...
+
+---
+
+name:            no_merge_impdef0
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: no_merge_impdef0
+    ; CHECK: S_NOP 0, implicit-def $sgpr0
+    ; CHECK: S_NOP 0
+    S_NOP 0, implicit-def $sgpr0
+    S_NOP 0
+
+...
+
+---
+
+name:            no_merge_impdef1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: no_merge_impdef1
+    ; CHECK: S_NOP 0
+    ; CHECK: S_NOP 0, implicit-def $sgpr0
+    S_NOP 0
+    S_NOP 0, implicit-def $sgpr0
+
+...
+
+---
+
+name:            no_merge_impdef_both
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; CHECK-LABEL: name: no_merge_impdef_both
+    ; CHECK: S_NOP 0
+    ; CHECK: S_NOP 0, implicit-def $sgpr0
+    S_NOP 0
+    S_NOP 0, implicit-def $sgpr0
+
+...