[PATCH] D64630: [DebugInfo] Address performance regression with r364515

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added inline comments.


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Comment at: lib/CodeGen/RegisterCoalescer.cpp:1978
+// See comment for CheckDbgValuesInBlock; this is a specialised copy for
+// when one coalesced register is a physical register.
+static void CheckDbgValuesInBlockForPhysReg(const SlotIndexes &Slots,
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aprantl wrote:
> ///
Not clear to me, just reading the description and the argument list, to understand if `Reg` is the physical register or the other register being coalesced.


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Comment at: lib/CodeGen/RegisterCoalescer.cpp:1982
+                                            const LiveInterval &RegLiveness,
+                                            unsigned Reg) {
+  SlotIndex BlockStart = Slots.getMBBStartIdx(MBB);
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I think we want Reg to be of type Register here (at least in the future, but maybe we can get it right from the start).


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Comment at: lib/CodeGen/RegisterCoalescer.cpp:2004
+    if (MI.isDebugValue() && !RegIsLive &&
+        MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == Reg) {
+      // If so, point the DBG_VALUE to $noreg
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Not sure if the old code cared much about it either, but I always wonder if we forget to consider sub registers when I see code that only looks at getReg() but not getSubReg() and not even mentions sub registers in any code comment. But since we are dealing with physical registers, then maybe getSubReg() is out-of-play here (although it is only one side of the coalescing pair that is physical).


Repository:
  rL LLVM

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  https://reviews.llvm.org/D64630/new/

https://reviews.llvm.org/D64630